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az23
Contributor
Contributor
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Registered: ‎05-31-2018

Reading PL DDR4 from R5?

Hi,

Is it possible to read PL DDR4 address spaces directly from the R5?

I can do it with a simple PL BRAM, but with the PL DDR4 address space, using 40 bit addressing, I cannot seem to access the memory.

I am trying to do something simple like:

u32 *bufferptr_ddr_pl = (u32 *) PL_DDR4_ADDRESS; //defined as 0x4 0000 0000

And then I read the data afterwards with some simple c code from the r5 firmware. Do I need some special connections or routing in Vivado to do this?

In linux, I can do a write to the same address with something like devmem 0x400000000 w 0x1.

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calebd
Moderator
Moderator
457 Views
Registered: ‎01-09-2019

@az23 

Looking in UG1085 page 80 talking about the R5, you can see that the R5 only has 32 bits to address.  https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

If you are doing a 40 bit addressing to the DDR, I don't think that full data is being passed on.  There are memory regions in the lower 32 bits of addressing that can access the PL (M_AXI_HPM0_FPD and M_AXI_HPM1_FPD).  The Address Map can be seen on page 225 of UG1085.

Thanks,

Caleb


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