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jcsistemas2001
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Registered: ‎12-18-2014

Reading data from DDR2 controller get ERROR:Pack:2811

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Hello All,

 

I'm working on a DDR2 controller based on MIG 3.6.1 on ISE 14.7 (nt64) on a FPGA xc3s1400a-4ft256 with a MT47H32M8BP-37E.

 

 

The DDR2 controller is working as expected. All the signals for read and write operations seems OK on the evaluation board. However, trying to read the data (using the DDR2 module output ddr2_user_output_data) the map process show the error ERROR:Pack:2811.

 

If following code is deleted, the error disappear:

 

	always @ (negedge ddr2_clk90_tb) begin
		if(ddr2_user_data_valid) begin
			dataout[31:16] <= ddr2_user_output_data; << this line cause the error
			dataout[15:0] <= dataout[31:16];
		end
		else begin
			dataout <= dataout;
		end
	end	

The previous code read the data on the negative edge of clk90 as suggested by UG086 (v3.6) on Figure 8-11 page 333.

 

More details about the error below:

 

ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=SLICE_X77Y87) which requires the combination of the symbols
   listed below to be packed into a single SLICEL component.

   The directed pack was not possible because: There are more than two function
   generators.
   The symbols involved are:
   	FLOP symbol
   "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo
   _0_wr_en_inst/delay_ff" (Output Signal =
   mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_
   0_wr_en_inst/din_delay)
   	LUT symbol
   "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo
   _1_wr_en_inst/dout01" (Output Signal =
   mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_
   1_wr_en_inst/dout0)
   	LUT symbol
   "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo
   _1_wr_en_inst/dout1" (Output Signal =
   mem_control/u_ddr2/top_00/data_path0/fifo_1_wr_en)
   	LUT symbol
   "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo
   _0_wr_en_inst/rst_dqs_delay_n1_INV_0" (Output Signal =
   mem_control/u_ddr2/top_00/data_path0/data_read_controller0/rst_dqs_delay_n)
   	FLOP symbol
   "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo
   _1_wr_en_inst/delay_ff_1" (Output Signal =
   mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_
   1_wr_en_inst/din_delay)

Mapping completed.
See MAP report file "Test7_map.mrp" for details.
Problem encountered during the packing phase.

 

Any suggestion to read the data from the controller or figure out the issue?

 

Thanks

 

Julio

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Accepted Solutions
vsrunga
Xilinx Employee
Xilinx Employee
14,670 Views
Registered: ‎07-11-2011

Hi,

 

I see that MIG generated ucf has different Slice locations for fifo_0_wr_en_inst and fifo_1_wr_en_inst

 

INST "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X1Y61;
INST "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X3Y61;

 

But in your overall design you tried to assign one SLICE location to two different instances which results in unplaceable condition for the tool.

 

Please comment out one of the below constarints in your Test7.ucf  so that tool will place the logic appropriately or assign them to to different locations and rerun the design, you can see that implementation will be successfull

 

INST "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X77Y87;
INST "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X77Y87;

 

 

Hope this helps

 

-Vanitha

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vsrunga
Xilinx Employee
Xilinx Employee
8,841 Views
Registered: ‎07-11-2011

Hi,

 

Double check if dataout is assigned twice may be in another module or somewhere else ?

 

Do refer below links on relavant discussions for more suggestions

 

http://forums.xilinx.com/t5/Implementation/Pack-2811-Error-with-RLOC-s/td-p/442354

 

http://forums.xilinx.com/t5/Implementation/Map-failed-with-Pack-2811-error-after-enabling-Global/td-p/270248

 

http://forums.xilinx.com/t5/Embedded-Development-Tools/ERROR-Pack-2811-Directed-packing-was-unable-to-obey-the-user/td-p/398795

 

 

Hope this helps

 

-Vanitha

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jcsistemas2001
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Registered: ‎12-18-2014

Hello Vanitha,

 

I double check dataout. 

 

dataout is defined as output reg [31:0] dataout, and is used on other modules (input port). On this module is used to load another register (other_register <= dataout). I don't see assigments. In any case, If I delete any deference to dataout the error is gone. 

 

Suggestions from others posts:

 

Map Optimization Strategy. Originally the project use "Speed". After turn off, the error still present. This is the only option that I could get from other posts. 

 

I also found that these errors differ on the possible cause:

 

 

  • The directed pack was not possible because: The clock signals don't agree.
  • The directed pack was not possible because: More than one pad symbol.
  • The directed pack was not possible because: There are more than two function generators. This is the same error that I have. On [1] the user need to change a picoblaze module to solve the problem. Can I do the same? I would not like to modified the internal design of the DDR2 controller.

Other suggestions?

 

Thanks

 

Julio

 

[1] http://forums.xilinx.com/t5/Synthesis/Keeping-Hierarchy-causes-packing-error-with-PicoBlaze-6/td-p/122850 

 

 

 

 

 

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jcsistemas2001
Visitor
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Registered: ‎12-18-2014

Any idea?

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vsrunga
Xilinx Employee
Xilinx Employee
8,805 Views
Registered: ‎07-11-2011

Hi,

 

Is this a standalone ISE design or do you have any proessor?

If it is standalone please upload your design for investigation, if it has microblaze as well then may be you need to check in EDK tools board as well.

 

Regards,

Vanitha

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jcsistemas2001
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Registered: ‎12-18-2014

Hi Vanitha,

 

It's a standalone ISE design to control two (2) external devices:

 

 

  • DDR2 memory
  • FTDI device (an USB controller)

Every device is manage by a module that include a state machine. The top module (Test7) use both modules (DDR & FTDI). When an external signal is received, the state machine on Test7:

 

 

  1. Write data to the DDR2
  2. Read data from the DDR 
  3. Send the same data to FTDI
  4. Wait for another trigger

I attached the complete folder (Test7) including the project file at: Test7\ddr2\user_design\par\test.xise

 

Attached files:

 

  • Design components (DDR2, FTDI and state machines)
  • Implementation details (IDE, board and project file)

Thanks for your interest,

 

Julio

 

design components.png
implementation details.png
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vsrunga
Xilinx Employee
Xilinx Employee
14,671 Views
Registered: ‎07-11-2011

Hi,

 

I see that MIG generated ucf has different Slice locations for fifo_0_wr_en_inst and fifo_1_wr_en_inst

 

INST "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X1Y61;
INST "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X3Y61;

 

But in your overall design you tried to assign one SLICE location to two different instances which results in unplaceable condition for the tool.

 

Please comment out one of the below constarints in your Test7.ucf  so that tool will place the logic appropriately or assign them to to different locations and rerun the design, you can see that implementation will be successfull

 

INST "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X77Y87;
INST "mem_control/u_ddr2/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X77Y87;

 

 

Hope this helps

 

-Vanitha

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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jcsistemas2001
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Registered: ‎12-18-2014

I follow your suggestions and the error is gone.

 

Thanks Vanitha! 

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