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Wolf9466
Observer
Observer
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Registered: ‎05-14-2021

Reasoning for the 900Mhz HBM2 clock limit

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I asked on Twitter, "What is the reasoning for the HBM clock limit of 900Mhz on Virtex Ultrascale+? I have some theories, but I'd like to ask directly." - and was advised to ask on this forum. Also a question on my mind - why was it made so difficult to clock it higher?

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ryana
Moderator
Moderator
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Registered: ‎11-28-2016

Hello @Wolf9466,

Yes, the HBM parts on Virtex UltraScale+ devices are capable of 1000MHz operation but the total solution cannot support those data rates across PVT and Data Sheet.  The expectation here is guaranteeing operation across the limits stated in DS923, across process variation,  while also meeting power rail and reference clock quality guidelines.  In order to meet those reliability guidelines the highest data rate for the HBM interface clock is 900MHz for -3 and -2 speed grade devices and 800MHz for -1 speed grade devices as stated in DS923.  See the screenshot below:
ds923_hbm_operating_rates.jpg

While it may be possible to manually change the PLL settings to get higher data rates there is a real chance across your sample size and operating environments some devices may not be able to maintain those data rates without error.  There is no user way to make these changes since it would violate what is officially supported by the solution and could cause Xilinx to take returns on parts which meet the Data Sheet operational expectations but fall out in your use case. It's also a support issue since allowing users to go beyond the supported use case could mean product fallout for your end customers, cause costly RMAs, and an overall bad impression of Xilinx products.

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

how fast would you like HBM to go ?

  

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Wolf9466
Observer
Observer
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Registered: ‎05-14-2021

Since I'm pretty sure the Ultrascale+ HBM parts are packing Samsung Aquabolt HBM2, a minimum of 1000Mhz, and possibly up to 1200Mhz (depending on the specific part/binning) at 1.2V.

 

However... another solution would just be to allow the user to decide the PLL parameters?

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

so I would suggest that the reason could be Xilinx selected the speed of the parts chosen to fit in with, the voltage they run at, the speed of the drivers / interconnect, the power dissipated and the speed of the logic used to drive them.

 

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Wolf9466
Observer
Observer
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Registered: ‎05-14-2021

Having used these in practice at 1100Mhz+ (and not just me)... I find this scenario a bit less likely, which is why I'm asking.

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kshimizu
Xilinx Employee
Xilinx Employee
961 Views
Registered: ‎03-04-2018

Hello @Wolf9466 ,

 

I think this is the specification.  I see the PG276, and it describes the frequency until 900MHz.  Xilinx evaluates the Max Frequency, so please we recommend using until 900MHz. 

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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Wolf9466
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Registered: ‎05-14-2021

In the Product Guide, yes. However, the actual HBM2 used in the Virtex Ultrascale HBM series is (correct me if I am wrong) Samsung Aquabolt, and it is specified for a higher frequency.

My question is, why is it underclocked? Also, why is it forced this way?

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ryana
Moderator
Moderator
787 Views
Registered: ‎11-28-2016

Hello @Wolf9466,

Yes, the HBM parts on Virtex UltraScale+ devices are capable of 1000MHz operation but the total solution cannot support those data rates across PVT and Data Sheet.  The expectation here is guaranteeing operation across the limits stated in DS923, across process variation,  while also meeting power rail and reference clock quality guidelines.  In order to meet those reliability guidelines the highest data rate for the HBM interface clock is 900MHz for -3 and -2 speed grade devices and 800MHz for -1 speed grade devices as stated in DS923.  See the screenshot below:
ds923_hbm_operating_rates.jpg

While it may be possible to manually change the PLL settings to get higher data rates there is a real chance across your sample size and operating environments some devices may not be able to maintain those data rates without error.  There is no user way to make these changes since it would violate what is officially supported by the solution and could cause Xilinx to take returns on parts which meet the Data Sheet operational expectations but fall out in your use case. It's also a support issue since allowing users to go beyond the supported use case could mean product fallout for your end customers, cause costly RMAs, and an overall bad impression of Xilinx products.

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Wolf9466
Observer
Observer
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Registered: ‎05-14-2021

 This is... a remarkably good answer. Thank you. I suppose that's the same reason why the APB registers are not publicly documented?

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barriet
Xilinx Employee
Xilinx Employee
773 Views
Registered: ‎08-13-2007

It is also possible that the limit here isn't the HBM2 itself but rather the Xilinx implementation of the HBM controller in the VU3xP/VU4xP - flanking the HBM across the SLR. It has to be guaranteed to work across PVT for the associated speed grade.

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ryana
Moderator
Moderator
772 Views
Registered: ‎11-28-2016

Hello @Wolf9466 ,

Yes, that's correct.  The register settings are automatically generated for the supported use cases. Exposing the register space details could lead to users generating their own settings and ending up in unsupported corners or potentially damaging parts because they felt confident, based on the information they had, they could push the parts past the stated limits.

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Wolf9466
Observer
Observer
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Registered: ‎05-14-2021

Understandable. I've got *most* of them figured out by now - but I think that poses enough of a barrier to entry that it won't cause issues for Xilinx. Again, thank you very much for your explanation!

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ryana
Moderator
Moderator
745 Views
Registered: ‎11-28-2016

Hello @Wolf9466 ,

Sure thing, glad I could put some closure to this.

Yes, I can imagine how much of a pain it was to go through that process but sometimes that's the approach to keep people within the supported use cases.

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