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AlexProulx
Visitor
Visitor
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Registered: ‎07-09-2020

Remove I/O BUF from MIG IP

Good Day,

 

I need to multiplex the signals coming out of the 7 Series MIG IP within the FPGA. However, as the IP is designed with integrated I/O BUF's, I am unable to place circuitry between the FPGA's I/Os and the MIG IP.

 

Is there anyway to bypass or remove those I/O BUF's? I am trying to avoid designing my own DDR controller from scratch to perform the task.

 

Options I am considering are as follows:

  1. Removing the I/O BUF from the IP in block design.
  2. Feeding the Output buffer to the Input buffer on the same IO BUFF in order to  re-insert the signal into the FPGA. However, even if possible, I believe this would create an issue for bi-directional signals such as DQS and DQ.
  3. Directly manipulating the netlist to remove I/O BUF. Not sure how this would work.

 

Thank you,

Alex

 

 

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rpr
Moderator
Moderator
355 Views
Registered: ‎11-09-2017

Hi

IP configuration doesn't provides bypass or remove those I/O BUF's.

MIG source code is not encrypted, generate the IP output products in global and modify the source code as per your requirement.

Regards
Pratap

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