I need to multiplex the signals coming out of the 7 Series MIG IP within the FPGA. However, as the IP is designed with integrated I/O BUF's, I am unable to place circuitry between the FPGA's I/Os and the MIG IP.
Is there anyway to bypass or remove those I/O BUF's? I am trying to avoid designing my own DDR controller from scratch to perform the task.
Options I am considering are as follows:
Removing the I/O BUF from the IP in block design.
Feeding the Output buffer to the Input buffer on the same IO BUFF in order to re-insert the signal into the FPGA. However, even if possible, I believe this would create an issue for bi-directional signals such as DQS and DQ.
Directly manipulating the netlist to remove I/O BUF. Not sure how this would work.