02-28-2021 02:58 AM
I have a FPGA program that has memory mapped registers. I write some data and do some analysis over time. Then I wish to reset the FPGA as if it were just reprogrammed . In other words, i want to clear all user data on the FPGA but keep the program when the board power is on. Is that possible? Board: Kintex Ultrascale KU040.
02-28-2021 07:32 AM
Memory mapped registers = memory. There are two options: internal BRAM (will be destroyed after reconfig) or external memory (not reset).
If you are using external DDR RAM and you reconfigure the FPGA, memory should retain its content unless the board resets it as well.
02-28-2021 08:59 AM
User data is stored in many places,
in the memory as said by @joancab
but also in the configuration of al the registers and logic in the circuit.,
The tools have no inherent knowledge as to what is "user data"
its up to you system design to separate any parts that you wan tot reset and those parts that can be left alone.
At the extrema ,its possible to do a partial reconfiguration,
its not for beginners, and its hard to get right,
but it is documented and can be done, so you could partition the user data and the none user data ,
At the end of the day, the FPGA can be re configured without cycling the power,
the FPGA will re load its logic etc from the configuration system , and everything will be reset back
02-28-2021 06:46 PM
In other words, i want to clear all user data on the FPGA but keep the program when the board power is on.
When you say "clear all user data" does this include the "memory mapped registers" which you referred to?
What you are describing is a reset of some kind. There are various mechanisms of resetting FPGAs.
One is a user implemented reset pin - when you write your RTL have each clocked process use this reset signal to set the flip-flop to a known value (the reset value). This can be used to clear all flip-flops and all pipeline registers in macro cells (like the DSP48 and the registers in the BRAMs), but not the memory elements - the BRAM and selectRAM (distributed RAM) contents.
In addition to any user implemented reset, there is the GSR (the Global Set/Reset). This is a signal that the FPGA uses during initialization (when the bitstream is downloaded) to initialize the state of all storage elements just before your design starts operating. This clears all flip-flops to their INIT value, and also sets the contents of all RAM cells to their initialization data (except UltraRAM, which can can only be cleared to 0).
Normally the GSR is invisible - it does what it does "under the hood" during the initialization phase of the FPGA. However, there is a mechanism of reasserting the GSR at a later date, by instantiating the STARTUP cell (STARTUPE3). The GSR pin of the STARTUPE3 is an input - if your RTL asserts this signal, the FPGA will enter the GSR state, and reinitialize all storage elements with the values that were provided by the bitstream. Once complete, the FPGA will return to the running state will all storage elements back at their initialization defaults.
03-01-2021 06:18 PM
@avrumw When you say "clear all user data" does this include the "memory mapped registers" which you referred to? Nope, registers will be there. I only want to clear the value.
Thanks everyone who replied here.
03-02-2021 03:42 AM
When yo do a configuration,
all internal logic with the exception of I think the URAM, is returned to its initial condition,
I dont think you have URAM, so thats not a problem,