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Visitor
Visitor
8,491 Views
Registered: ‎12-08-2014

Reset dependency between DDR4 interfaces

Hi,

 

I have a Kintex ultrascale design with 2 DDR4 SDRAM interfaces. The design is controlled and monitored using a VIO core for each DDR4 interface. The VIOs control the DDR4 sys_rst inputs, and monitor the init_calib_complete outputs.

 

The 2 DDR4 SDRAM interfaces share a common c0_sys_clk_i, and are located over IO banks 46,47,48, with bank 47 shared between the two.

 

On power up, both interfaces complete calibration OK. If I reset both interfaces at the same time everything is still ok.

If I reset one interface only, then it will not complete calibration until the other interface is reset.

If I hold one interface in reset, then the other will reset and complete cal OK.

 

Can anyone suggest where this dependency is and if it is removable?

 

Thanks

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Xilinx Employee
Xilinx Employee
8,415 Views
Registered: ‎07-11-2011

@kencrocker, In which bank sys_rst and ddr3_reset pins of both the controllers are lcoated?

If calibration failed in which stage did it stuck? 

What are all the siganls thaat are connected to shared bank-47?

 

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Visitor
Visitor
8,412 Views
Registered: ‎12-08-2014

Hi vsrunga

 

The sys_rst pin for each MIG controller is generated from a VIO core output.

 

The first MIG controller DDR4 reset output pin is in bank 46. The second is in bank 48.

 

When I reset one or more MIG controllers using their VIO reset in hardware manager, the MIG state and calibration state does not always indicate what is happening correctly. In this case it is not updating at all and is providing no useful information.

 

The VIO cores monitor the MIG controller init calib complete, and after reset we can see activity on them. If all is well then they go low and then high after a second or so indicating calibration is complete. If all is not well then they go low and stay low until the other bank is reset.

 

I have attached our schematic fragment for bank 47.

 

Thanks

 

Ken

bank47.JPG
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Explorer
Explorer
8,354 Views
Registered: ‎10-19-2012

Let me ask you a question, do you intend to use each DDR4 chip as a separate interface, or you intend to use both chips in a single interface ? Also I don't understand if each of the DDR4 chips has a init_calib_complete signal or if there is one for both of them. It is clear that you have one reset for each of the chips.

If you intend to use them as separate interfaces then generate two different cores for each DDR4 chip. Each will have reset and calib_complete and should be independent of each other. If you want this configuration, special care should be taken for the clocking architecture, which in this case you don't specify quite clearly.

If you want to have a single interface for both chips, then it makes sense that calibration should be dependent on both chips (single init_calib_complete for both chips, and a single reset for both)

 

In each case, bank sharing restrictions may apply, and you should take special care about that.

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