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Adventurer
Adventurer
761 Views
Registered: ‎01-20-2017

Running DRC leads to PLIDC #1 related to memory controller signal

I'm designing a custom board using a Kintex-7 xc7k160tffg676-2 device in Vivado 2016.1.   I have a relatively simple design with a Microblaze processor connected to a memory controlly (generated via MIG).  After synthess and placing some ancillary input/output ports in my XDC file, I ran 'Report DRC' using the 'default' Vivado Rule Decks.  I'm getting the error:

PLIDC #1 IDELAYCTRL cells have been found to be associated with IODELAY_GROUP 'DESIGN_1_MIG_1_0_IODELAY_MIG0', but the design does not contain IODELAY cells associated with this IODELAY_GROUP. 

I see from other posts that I might need to add a line to my constraints file (something like 'set_property IODELAY_GROUP something-something-something'), but I'm unsure what I'm actually doing and how to determine exactly how to specify this.  Can anyone explain what is required to overcome this error?

One other piece of information:  I am able to successfully implement and generate the bitstream for this project.

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8 Replies
Teacher xilinxacct
Teacher
729 Views
Registered: ‎10-23-2018

Re: Running DRC leads to PLIDC #1 related to memory controller signal

@efpkopin 

Is this one of the posts you saw? (Different FPGA family, but may give some insight)

https://forums.xilinx.com/t5/Virtex-Family-FPGAs/iodelay-group-cells-have-been-found-but-have-no-idelayctrl/m-p/753986#M25806

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed. :-)

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Xilinx Employee
Xilinx Employee
717 Views
Registered: ‎05-08-2012

Re: Running DRC leads to PLIDC #1 related to memory controller signal

Hi @efpkopin 

MIG is using delay elements (IDELAYs or ODELAYs). When I/ODELAYs are used, an IDELAYCTRL is needed to provide the reference clock. Both the I/ODELAY and IDELAYCTRL would need to be grouped together. In this case, the error is indicating that there is no I/ODELAYs in the design using the same group property "IODELAY_GROUP".

I would try opening the synthesized design. Are there both IDELAYCTRLs and I/ODELAYs? If you click on the properties tab for these, do they have the same "IODELAY_GROUP" property value? If so, I would run opt_design from the Tcl console, and check again. opt_design might be removing these. If this is the case, you would likely need to adjust the connectivity so that they are connected properly.


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

 

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
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Adventurer
Adventurer
703 Views
Registered: ‎01-20-2017

Re: Running DRC leads to PLIDC #1 related to memory controller signal

@marcb  As you suggest, I opened the synthesized design and used the Find window to search Cells by 'NAME' for both *idelay and then *odelay (see attached) I found a descrepancy when looking at the two IDELAYCTRL cells when searching for Cell NAMES of  '*idelay '  The first cell *idelayctrl_300_400 had an IODELAY_GROUP of DESIGN_1_MIG_1_0_IODELAY_MIG1 while the 2nd cell *idelayctrl_200 had an IODELAY_GROUP of DESIGN_1_MIG_1_0_IODELAY_MIG0.  I scanned through all the other entries that came up in this search and anytime I saw an IODELAY_GROUP property, it was listed as the former, namely DESIGN_1_MIG_1_0_IODELAY_MIG1.  So not knowing anything else (but using the form of the solution presented at https://forums.xilinx.com/t5/Virtex-Family-FPGAs/iodelay-group-cells-have-been-found-but-have-no-idelayctrl/m-p/753986#M25806), I put into my constraints file the command:

set_property IODELAY_GROUP DESIGN_1_MIG_1_0_IODELAY_MIG1 [get_cells -hierarchical "*u_idelayctrl_200*"]

I resynthesized and ran the DRC and now I get *two* errors!  In fact I also get warnings related to idelayctrl:

These are the errors I'm getting:

PLIDC-3  
PLIDC #1 IDELAYCTRL cells 'design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/idelayctrl_gen_1.u_idelayctrl_300_400' and 'design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/u_idelayctrl_200' have same IODELAY_GROUP 'DESIGN_1_MIG_1_0_IODELAY_MIG1' but their REFCLK signals are different 
PLIDC #2 IDELAYCTRL cells 'design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/idelayctrl_gen_1.u_idelayctrl_300_400' and 'design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/u_idelayctrl_200' have same IODELAY_GROUP 'DESIGN_1_MIG_1_0_IODELAY_MIG1' but their RST signals are different 

And these are the warnings that seem related:

PLIDC-14  
PLIDC #1 The BITSLICE cell IDELAYCTRL design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/idelayctrl_gen_1.u_idelayctrl_300_400 REFCLK pin should be driven by the same clock net as the associated ISERDES design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.iserdesdq CLK or CLKDIV pin. 
PLIDC #2 The BITSLICE cell IDELAYCTRL design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/u_idelayctrl_200 REFCLK pin should be driven by the same clock net as the associated ISERDES design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.iserdesdq CLK or CLKDIV pin. 

By the warnings, it would almost seem like these idelayctrl's really should be different IODELAY_GROUPs.  This does not seem to be the way to fix the problem...

Any ideas?

 

when_searching_for_idelay.PNG
when_searching_for_odelay.PNG
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Xilinx Employee
Xilinx Employee
689 Views
Registered: ‎05-08-2012

Re: Running DRC leads to PLIDC #1 related to memory controller signal

Hi @efpkopin 

 

Can you try the following from the open synthesized design and post the results? This should show the grouping before and after opt_design and give use a better understanding of the problem.

set cells [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.iodelay.* || PRIMITIVE_TYPE =~ IO.idelayctrl.* } ]
foreach i $cells {puts "GROUP: [get_property IODELAY_GROUP [get_cells $i]] PRIMITIVE: [get_property REF_NAME [get_cells $i]] NAME: $i"}
opt_design
foreach i $cells {puts "GROUP: [get_property IODELAY_GROUP [get_cells $i]] PRIMITIVE: [get_property REF_NAME [get_cells $i]] NAME: $i"}

 


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
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Adventurer
Adventurer
655 Views
Registered: ‎01-20-2017

Re: Running DRC leads to PLIDC #1 related to memory controller signal

@marcb  I ran those commands (this is w/ the synthesized design with the command: 

set_property IODELAY_GROUP DESIGN_1_MIG_1_0_IODELAY_MIG1 [get_cells -hierarchical "*u_idelayctrl_200*"]

present in the constraints.  

It seems to me that the result is identical before and after 'opt_design'.  Here is the specific output while entering those commands:

set cells [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ IO.iodelay.* || PRIMITIVE_TYPE =~ IO.idelayctrl.* } ]
design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/idelayctrl_gen_1.u_idelayctrl_300_400 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/u_idelayctrl_200 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[9].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2 design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/i...
foreach i $cells {puts "GROUP: [get_property IODELAY_GROUP [get_cells $i]] PRIMITIVE: [get_property REF_NAME [get_cells $i]] NAME: $i"}
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYCTRL NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/idelayctrl_gen_1.u_idelayctrl_300_400
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYCTRL NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/u_idelayctrl_200
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[9].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[9].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.597 . Memory (MB): peak = 2364.520 ; gain = 0.000
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'VIRTUAL_clk_out1_design_1_clk_wiz_0_0' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [C:/gggg/DpRxSst_DevKit_Mark1_early_just_Mblaze_n_MIG/hw/project_1/project_1.srcs/constrs_1/new/board_constraints.xdc:11]
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task
Implement Debug Cores | Checksum: 130c35a48

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 48 inverter(s) to 167 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1f0bc037c

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2391.883 ; gain = 0.313

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 2 inverter(s) to 2 load pin(s).
INFO: [Opt 31-10] Eliminated 1630 cells.
Phase 2 Constant Propagation | Checksum: 1af857728

Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2391.883 ; gain = 0.313

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 6541 unconnected nets.
INFO: [Opt 31-11] Eliminated 4359 unconnected cells.
Phase 3 Sweep | Checksum: 149d38052

Time (s): cpu = 00:00:28 ; elapsed = 00:00:27 . Memory (MB): peak = 2391.883 ; gain = 0.313

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.174 . Memory (MB): peak = 2391.883 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 149d38052

Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2391.883 ; gain = 0.313

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Constraints 18-483] create_clock: no pin(s)/port(s)/net(s) specified as objects, only virtual clock 'VIRTUAL_clk_out1_design_1_clk_wiz_0_0' will be created. If you don't want this, please specify pin(s)/ports(s)/net(s) as objects to the command. [C:/gggg/DpRxSst_DevKit_Mark1_early_just_Mblaze_n_MIG/hw/project_1/project_1.srcs/constrs_1/new/board_constraints.xdc:11]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 60 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 5 Total Ports: 120
Number of Flops added for Enable Generation: 3

Ending PowerOpt Patch Enables Task | Checksum: 1b1f5b197

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.201 . Memory (MB): peak = 2803.934 ; gain = 0.000
Ending Power Optimization Task | Checksum: 1b1f5b197

Time (s): cpu = 00:00:38 ; elapsed = 00:00:17 . Memory (MB): peak = 2803.934 ; gain = 412.051
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:01:16 ; elapsed = 00:00:50 . Memory (MB): peak = 2803.934 ; gain = 439.414
foreach i $cells {puts "GROUP: [get_property IODELAY_GROUP [get_cells $i]] PRIMITIVE: [get_property REF_NAME [get_cells $i]] NAME: $i"}
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYCTRL NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/idelayctrl_gen_1.u_idelayctrl_300_400
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYCTRL NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_iodelay_ctrl/u_idelayctrl_200
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[9].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[0].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/input_[9].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[1].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[2].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[3].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[4].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[5].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[6].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[7].iserdes_dq_.idelay_finedelay_dq.idelaye2
GROUP: DESIGN_1_MIG_1_0_IODELAY_MIG1 PRIMITIVE: IDELAYE2_FINEDELAY NAME: design_1_i/memory_subsystem/mig_1/u_design_1_mig_1_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/input_[8].iserdes_dq_.idelay_finedelay_dq.idelaye2
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Xilinx Employee
Xilinx Employee
645 Views
Registered: ‎05-08-2012

Re: Running DRC leads to PLIDC #1 related to memory controller signal

Hi @efpkopin 

After taking a look at the results of the IDELAY grouping before and after, there is no change. However, There are two IDELAYCTRLs, but only 1 IODELAY_GROUP property specified "DESIGN_1_MIG_0_IODELAY_MIG1". With two IDELAYCTRLs, I would expect a second set of I/ODELAY cells. This looks to be an issue with the MIG setup. 


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idelayctr_grouping.png
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Adventurer
Adventurer
606 Views
Registered: ‎01-20-2017

Re: Running DRC leads to PLIDC #1 related to memory controller signal

@marcb Are you saying that I might have made some kind of mistake when generating the MIG for my project? Or is it a bug in the MIG software associated with Vivado?


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Xilinx Employee
Xilinx Employee
579 Views
Registered: ‎05-08-2012

Re: Running DRC leads to PLIDC #1 related to memory controller signal

Hi @efpkopin 

This post was moved to the Memory Interfaces board. I think this would be a better place to understand how a MIG IP could be setup to where there are two controllers (IDELAYCTRL), but only one set of delays (IDELAY). This is what is causing the error.

 

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