I've used MIG to generate a DDR2 memory controller with 4 ports (0,2,3,4) with round robin arbitration, but am a bit confused with the generated code.
The top level of the MIG design has the following for the ARB_TIME_SLOT settings, and that looks as expected:
constant C1_ARB_TIME_SLOT_0 : bit_vector(11 downto 0) := o"0234";
constant C1_ARB_TIME_SLOT_1 : bit_vector(11 downto 0) := o"2340";
constant C1_ARB_TIME_SLOT_2 : bit_vector(11 downto 0) := o"3402";
constant C1_ARB_TIME_SLOT_3 : bit_vector(11 downto 0) := o"4023";
constant C1_ARB_TIME_SLOT_4 : bit_vector(11 downto 0) := o"0234";
constant C1_ARB_TIME_SLOT_5 : bit_vector(11 downto 0) := o"2340";
constant C1_ARB_TIME_SLOT_6 : bit_vector(11 downto 0) := o"3402";
constant C1_ARB_TIME_SLOT_7 : bit_vector(11 downto 0) := o"4023";
constant C1_ARB_TIME_SLOT_8 : bit_vector(11 downto 0) := o"0234";
constant C1_ARB_TIME_SLOT_9 : bit_vector(11 downto 0) := o"2340";
constant C1_ARB_TIME_SLOT_10 : bit_vector(11 downto 0) := o"3402";
constant C1_ARB_TIME_SLOT_11 : bit_vector(11 downto 0) := o"4023";
Then when I go down to the memc1_wrapper.vhd file it maps them as:
constant ARB_TIME_SLOT_0 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_0(11 downto 9) & C_ARB_TIME_SLOT_0(8 downto 6) & C_ARB_TIME_SLOT_0(5 downto 3) & C_ARB_TIME_SLOT_0(2 downto 0));
constant ARB_TIME_SLOT_1 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_1(11 downto 9) & C_ARB_TIME_SLOT_1(8 downto 6) & C_ARB_TIME_SLOT_1(5 downto 3) & C_ARB_TIME_SLOT_1(2 downto 0));
constant ARB_TIME_SLOT_2 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_2(11 downto 9) & C_ARB_TIME_SLOT_2(8 downto 6) & C_ARB_TIME_SLOT_2(5 downto 3) & C_ARB_TIME_SLOT_2(2 downto 0));
constant ARB_TIME_SLOT_3 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_3(11 downto 9) & C_ARB_TIME_SLOT_3(8 downto 6) & C_ARB_TIME_SLOT_3(5 downto 3) & C_ARB_TIME_SLOT_3(2 downto 0));
constant ARB_TIME_SLOT_4 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_4(11 downto 9) & C_ARB_TIME_SLOT_4(8 downto 6) & C_ARB_TIME_SLOT_4(5 downto 3) & C_ARB_TIME_SLOT_4(2 downto 0));
constant ARB_TIME_SLOT_5 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_5(11 downto 9) & C_ARB_TIME_SLOT_5(8 downto 6) & C_ARB_TIME_SLOT_5(5 downto 3) & C_ARB_TIME_SLOT_5(2 downto 0));
constant ARB_TIME_SLOT_6 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_6(11 downto 9) & C_ARB_TIME_SLOT_6(8 downto 6) & C_ARB_TIME_SLOT_6(5 downto 3) & C_ARB_TIME_SLOT_6(2 downto 0));
constant ARB_TIME_SLOT_7 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_7(11 downto 9) & C_ARB_TIME_SLOT_7(8 downto 6) & C_ARB_TIME_SLOT_7(5 downto 3) & C_ARB_TIME_SLOT_7(2 downto 0));
constant ARB_TIME_SLOT_8 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_8(11 downto 9) & C_ARB_TIME_SLOT_8(8 downto 6) & C_ARB_TIME_SLOT_8(5 downto 3) & C_ARB_TIME_SLOT_8(2 downto 0));
constant ARB_TIME_SLOT_9 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_9(11 downto 9) & C_ARB_TIME_SLOT_9(8 downto 6) & C_ARB_TIME_SLOT_9(5 downto 3) & C_ARB_TIME_SLOT_9(2 downto 0));
constant ARB_TIME_SLOT_10 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_10(11 downto 9) & C_ARB_TIME_SLOT_10(8 downto 6) & C_ARB_TIME_SLOT_10(5 downto 3) & C_ARB_TIME_SLOT_10(2 downto 0));
constant ARB_TIME_SLOT_11 : bit_vector(17 downto 0) := ("000" & "000" & C_ARB_TIME_SLOT_11(11 downto 9) & C_ARB_TIME_SLOT_11(8 downto 6) & C_ARB_TIME_SLOT_11(5 downto 3) & C_ARB_TIME_SLOT_11(2 downto 0));
This is where I get confused, as according to UG388 this appears to be setting port 0 as the highest priority for all time slots. Here is the description from ug388 for the ARB_TIME_SLOT values:
These 6-digit octal (18-bit) values set the port priority for each time slot.
Possible Values:
For example, C_ARB_TIME_SLOT0 = 18'o012345 (sets Port 0 with the highest priority down to Port 5 with the lowest
priority).
Can anyone confirm if the problem is with ug388, or MIG, or am I just getting confused?
