11-10-2011 12:20 AM
I am currently working on a project in ISE 12.4, which includes a Spartan 6 (XC6SLX75) and a block of Micron's DDR3 SDRAM (MT41J64M16).
I have used the MIG 3.61 to generate to core and then I started of by modifying the example design to fit the platform that I am working on to insure that everything works as planned.
I then ran the simulation in ISim which works as expected, both calibration and the following reads/writes of the traffic generator.
My problem occurs when I am synthesizing the project, the following timing constraint is not meet.
For all of the other clk's timing is met.
I have used the example design before in a LX9 using LPDDR, but at some lower frequencies, and the design worked like a charm.
My design has the following settings.
Are there any known problems with the example design when using larger FPGA's and higher frequencies?
The following has been changed to see if timing could be met.
I have changed the design properties to Timing instead of Balanced and added TIG to calib_done, error and the reset signal.
I have assigning the PLL being used according to:
I have tried splitting the clk signal, even though this should only apply to Verilog designs, MIG 3.70 and so on:
All of the above have gotten the timing score down a bit, but timing is still not met.
Hope somebody can help me and that I did not forget any important info.
Thanks in advance
11-10-2011 06:33 AM
If you remove the .xcf file for synthesis and only use the UCF does the design pass timing in implementation?
Also you only need to constrain the input clock to the PLL and not the output clocks. The tools might incorrectly analyze cross-clock domain paths if only the output clocks are defined since the tools won't know they are related.
Lastly, I would double check that you are still meeting the clocking requirements and have followed everything required for changing the input clock frequency:
11-10-2011 06:45 AM
In the example designs, clk0 (the clk which is failing for you) is the user clock, which you indicate you've set to 200 MHz. In the default example (at least in MIG 3.8), with the DDR3 set to 400 MHz (I assume you must also be using -3 parts, necessary for this DDR3 clock rate), the default user clk (clk0) is set to 50 MHz, 1/16 of the DDR3 bit rate clock (800 MHz).
Here are the default settings:
C3_MEMCLK_PERIOD : integer := 2500;
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
C_CLKOUT0_DIVIDE : integer := 1;
C_CLKOUT1_DIVIDE : integer := 1;
C_CLKOUT2_DIVIDE : integer := 16;
C_CLKOUT3_DIVIDE : integer := 8;
C_CLKFBOUT_MULT : integer := 2;
I haven't built their example, but I do know that it is quite possible to create logic that won't meet timing at 200 Mhz in the Spartan6. Perhaps you've just been overly optimistic about how fast their example will run. They may default to 50 MHz for good reason.
I would recommend changing your clk0 divider to set the user clock at 100 MHz.
Since you've already been modifying the clocks, I would also check the timing report, if you haven't already, to make sure the clock periods you've set are what you think they are.
11-11-2011 06:53 AM
Hi again and thanks for the quick replies
I am not quite sure where you want me to remove the .xcf file from?
Sorry if this something I should know :-)
To conclude on the other things in your reply, I do not have any additional constraints to my clk's, only on the input clk, which should be sufficient.
And I have changed everything accordingly to the 2 links, so I believe that it should be okay.
When selecting the user logic clock frequency and using more than one port, how should the calculation be made?
E.g. when I am using 2x64 bit ports should the equation be (32/64) * 400 MHz = 200 MHz, as if only solving the equation for one port.
Or should the two ports be added together giving the following equation (32/128) * 400 MHz = 100 MHz
I made the assumption that the first one was the correct one, but I could be wrong.
You are correct in your assumptions. I am used a -3 speedgrade and the default is a 50 MHz clock to the userlogic.
I have already checked the timing and my clocks are set as expected.
It should be noted that if I set clk0 to 100 MHz, my timing constraints are met just fine.
I just made the assumption that the example design would meet the timing constraints when using supported frequencies, but that might not be the case.
11-11-2011 10:12 AM
I would categorize 200 MHz as definitely in the range that is not guaranteed to meet timing, it all depends on how it's written.
I have plenty of code that works at 200 MHz, even in a -2 part, but it's carefully written. Sloppy code at that speed will easily fail timing. By lowering to 100 MHz, you have a lot more leeway. At 50 MHz, you almost have to intentionally write bad code to fail. :smileywink:
11-13-2011 07:01 AM
Yeah, I guess you're right. I just thought that it was written in such matter that it would support these frequencies, but I probably need to lower the frequency that I am using.