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Visitor
Visitor
655 Views
Registered: ‎01-09-2019

SDRAM IP bug

I tried including the DDR3 SDRAM IP (ARTY-7) into the block design and it crashed my Vivado software.
I'm using a licenced copy of Vivado Design Suite locked to Arty-7 FPGA.

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Moderator
Moderator
610 Views
Registered: ‎02-11-2014

Re: SDRAM IP bug

Hello @suyash01,

Thank you for providing a video showing your issue. Which specific build of Windows 10 are you using? We currently support the Windows 10.0 1803 update (64-bit) and the Windows 10.0 1809 Update (64-bit). Also which rev of the digilent board files are you using? I just downloaded the master branch from https://github.com/Digilent/vivado-boards/ to run my testing, but I could not reproduce the crash.

Also there should be a crash log located in %APPDATA%\Xilinx\Vivado. It should be the latest/newest hs_err_pid*.log file located in there. Please send over the log file so we can look into the crash better.

Also are you using a Webpack, Design Edition, or System Edition Install for Vivado 2018.3?

Thanks,
Cory

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Visitor
Visitor
586 Views
Registered: ‎01-09-2019

Re: SDRAM IP bug

My Windows version is: Windows 10.0 1803 (64-bit)

I'm using the Arty-7 35t cp324

Also, I'm using the Design Edition install for Vivado 2018.3

I've attached the error log files below.

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Moderator
Moderator
500 Views
Registered: ‎02-11-2014

Re: SDRAM IP bug

Hello @suyash01,

Sorry for the delay. After re-watching your video, I can see that you have a space in your project name/path. Please create a project without a space in the name and then retry adding MIG to IPI.

Thanks,
Cory

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Moderator
Moderator
462 Views
Registered: ‎02-11-2014

Re: SDRAM IP bug

Hello @suyash01,

I have run some tests recently. I went through your flow in Vivado 2018.2 and ran into no issues with a space in the project name / directory.

I went through the same test in Vivado 2018.3 and I didn't crash but I ran into an error exactly like @vkampen ran into in the following thread https://forums.xilinx.com/t5/Memory-Interfaces/MIG-v4-2-Vivado-2018-3-pin-out-validation-is-too-strict-amp/td-p/922026/page/2. The workaround is to remove the spaces from the project.

I will file a change request to get this issue resolved and then we will include the fix in https://www.xilinx.com/support/answers/71898.html as rev2 of the same patch.

Thanks,
Cory

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