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mnsgs
Observer
Observer
450 Views
Registered: ‎05-23-2017

Selecting the interacting UART for the zynq DDR memory test (zynq_dram_test)

Hi,

We have a design which enables both of the zynq 7000 PS UARTS, however, initially only the secondary of the two is available for connection. We would thus like to be capable of running the DDR memory test (https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/zynq_dram_test) using the secondary UART for interaction instead of the primary. Is this somehow configurable?

Thanks,
Martin

2 Replies
abouassi
Moderator
Moderator
364 Views
Registered: ‎03-25-2019

Hi @mnsgs,

You can change which UART to set from the BSP settings.

If you are using Vitis, then from your Platform project, double click on the platform.spr:

abouassi_0-1624643317442.png


then click, on the "Board Support Package" under your application related domain:

abouassi_1-1624643408134.png


Then Click on "Modify BSP Settings":

abouassi_2-1624643441780.png


You will find the UART setting as shown below:

abouassi_3-1624643480786.png

After applying the changes, don't forget to rebuild your platform project and your system project.

Best regards,
Abdallah
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mnsgs
Observer
Observer
247 Views
Registered: ‎05-23-2017

Hi @abouassi ,

Thank you very much for the prompt response and apologize for my late reply. For the time being we are at XSDK 2019.2, and render the application through the HSI commands:

set board nv3
set hwdsgn [openhw $board/system.hdf]
hsi generate_app -hw $hwdsgn -os standalone -proc ps7_cortexa9_0 -app zynq_dram_test -compile -dir $board/memtest
file rename -force $board/memtest/executable.elf $board/memtest.elf

and as a consequence I first need to familiarize myself with the GUI. I assume there is no way of changing it through the code?

Kind regards,

Martin

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