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williamsf2
Observer
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Registered: ‎01-14-2015

Setting up Micron DDR4 (MT53E128M32D2DS-53) with a zynq ultrascale XAZU3EG-1SFVA625I


Hi, Im trying to set up a Micron DDR4 (MT53E128M32D2DS-53) with a zynq ultrascale XAZU3EG-1SFVA625I and I'm struggling to extract all the info from the datasheet. Wondered if anyone could help who'd been through this pain before?


The settings I need are:-


Device frequency Mhz = ?
Speed bin = LPDDR4 ?
RAS to CAS delay (cycles) = ?
Precharge Time (cycles) = ?
tRC (ns) = ?
tRAS Min (ns) = ?
tFAW (ns) = ?
DRAM device capacity ( per 32bit channel) = ?
Row Address count bits = ?

Any help would be most appreciated...
Thanks

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rpr
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Registered: ‎11-09-2017

Hi @williamsf2 

MT53E128M32D2DS-53 - Dual-Die, Dual-Channel - 4Gb - 4096Mb - 512MB

XAZU3EG-1SFVA625I - Dual Die phy rate is 1000 - 1866 Mb/s

Refer to core timing parameters page no 262 - Memory data sheet.

Device frequency Mhz = 800
Speed bin = LPDDR4 1600
RAS to CAS delay (cycles) = 15
Precharge Time (cycles) = 17
tRC (ns) = 63
tRAS Min (ns) = 42
tFAW (ns) = 40
DRAM device capacity ( per 32bit channel) = 4096
Row Address count bits = 14

Regards
Pratap

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williamsf2
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Registered: ‎01-14-2015

Many thanks Pratap.

Just trying to understand where you got the information from on pg262?

Could you explain how you came to these figures? Also the device is 535ps what is this value?

Device frequency Mhz = 800  => So device freq 800Mhz/1.25nS where doe it say that.
Speed bin = LPDDR4 1600
RAS to CAS delay (cycles) = 15 => so is this 18ns/1.25ns?
Precharge Time (cycles) = 17 => which is this?
tRC (ns) = 63 => not sure?
tRAS Min (ns) = 42  =>should be max?
tFAW (ns) = 40 ok...
DRAM device capacity ( per 32bit channel) = 4096 => not sure?
Row Address count bits = 14

Many thanks again for the help...

 

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