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Observer
Observer
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Registered: ‎03-05-2019

Simulating DDR3 Memory with MIG - Stuck on Calibration

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I would like to run a behavioral simulation of DDR3 memory provided by MIG 7series 4.2. I'm working with Vivado 2019.2.

My simulation (using Vivado's simulator) gets stuck during initial calibration. The u_ddr_phy_init module advances to the INIT_PI_PHASELOCK_READS state, but does not progress further, and I can see the pi_phase_locked_err signal go high. The pi_phaselock_start signal goes high, but as far as I can tell from my analysis of the RTL, it doesn't drive anything except for a dbg signal. From what I can tell, they u_ddr_phy_init module is waiting on the pi_calib_rank_done signal from u_ddr_phy_dqs_found_cal_hr module, which never gets emitted.

Has anyone encountered this before? Any suggestions of further troubleshooting steps I can take?

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Moderator
Moderator
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Registered: ‎11-09-2017

Re: Simulating DDR3 Memory with MIG - Stuck on Calibration

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Hi @nkraemer 

Are you looking memory device available over MIG or custom memory part?

If it is from MIG ? then generate example design, right click on IP and select example design. If issue reproduced over example design then attach your .xci file, i mean IP configuration file. We will look from there.

Regards
Pratap

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Moderator
Moderator
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Registered: ‎11-09-2017

Re: Simulating DDR3 Memory with MIG - Stuck on Calibration

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Hi @nkraemer 

Are you looking memory device available over MIG or custom memory part?

If it is from MIG ? then generate example design, right click on IP and select example design. If issue reproduced over example design then attach your .xci file, i mean IP configuration file. We will look from there.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.

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Observer
Observer
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Registered: ‎03-05-2019

Re: Simulating DDR3 Memory with MIG - Stuck on Calibration

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Thanks for the help @rpr. This was with an memory device available from MIG. When I created the example design and simulated it, things worked normally. I believe I had incorrectly instatiated the DDR model in my original testbench.

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