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Participant
Participant
3,595 Views
Registered: ‎09-11-2010

Simulation error HDLCompiler:661 in mcb_raw_wrapper.v

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I included a MIG 3.3 IP in my project for SP605 development board using ISE11.5.  The design synthesizes fine but when I attempt to perform behavioral simulation I receive a HDLCompiler:661 errors in mcb_raw_wrapper.v like the ones listed below.  I get a total of 18 messages and the compile terminates with too many messages.  It appears that it is getting the error on every input port in mcb_raw_wrapper.v.

 

Line 264: Non-net port sysclk_2x cannot be of mode input

Line 265: Non-net port sysclk_2x_180 cannot be of mode input

 

Since the errors are happening within code generated by the IP I am not sure how to resolve the issue.  If I walk down the modules everything appears to be defined correctly

 

Any help you can provide would be appreciated.

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Participant
Participant
3,954 Views
Registered: ‎09-11-2010

I must have modified one of the other MIG files by mistake when customizing the memc3_infrastructure.v file for the SP605 board.  I regenerated the core which resolved the problem.

 

Thanks for your help

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Xilinx Employee
Xilinx Employee
3,588 Views
Registered: ‎08-16-2007

THe first thing I would check is that you have compiled the behavioral models for the correct version of ISE and that the MIG IP version is also matches with the same release.

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Participant
Participant
3,955 Views
Registered: ‎09-11-2010

I must have modified one of the other MIG files by mistake when customizing the memc3_infrastructure.v file for the SP605 board.  I regenerated the core which resolved the problem.

 

Thanks for your help

View solution in original post

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