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Contributor
Contributor
259 Views
Registered: ‎09-13-2019

Simulation not working in DDR example design

I create the example design for a ddr3 interface in a folder in my home directory (windows 10, vivado 2019.1). The example design opens up and when I click "Run simulation" I get the following error message popup from vivado:

Unable to open file '' because file does not have read permission. Would you like to open the directory instead?

Every other example design for other IPs I opened up I could simulate fine.

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3 Replies
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Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎08-21-2007

回复: Simulation not working in DDR example design

Are you running simulation within Vivado or third-party simulator?

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Contributor
Contributor
216 Views
Registered: ‎09-13-2019

回复: Simulation not working in DDR example design

Running it in Vivado.

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74 Views
Registered: ‎12-18-2019

回复: Simulation not working in DDR example design

I have a problem similar to dimitris78.

I was able to simulate the block memory when instantiated in a module lower in the hierarchy, but when I instantiate that lower module into another module and try to simulate it I get the following message:

"Unable to open file 'blk_mem_gen_v8_4.v' because file does not have read permission. Would you like to open the directory instead?"

When I choose to open the directory, it won't because: "A background task is running. Please wait until it completes and try again."  The background task never completes (it's waiting for the first message to be cleared.)  I've tracked down all instances of blk_mem_gen_v8_4.v and changed the permissions to "Full Control", which didn't help.

Any clues would be appreciated.

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