After generating a core for DDR2 using MIG (ISE 11.5, MIG v3.3, DDR2: MT47H32M16 (as on Spartan-3AN Start Kit)) I created a testbench in order to simulate the behaviour; it all works quite fine, but I still have a problem with the command-signals ISim shows:
Referring to the manual of the memory-chip I analyzed the init-sequence and the first read-command; but while doing so I wondered that cntrl0_ddr2_cs_n is always "0", in fact logic H. But this does not lead to any read command (which can be seen on Table 36 in the memory-datasheet).
Where is the error placed? Somewhere in the simulation or rather in my mind?
After studying the simulation for many times I also have a problem concerning the burst-length; as seen on figure 34 (MR Definition) in the datasheet of the memory, the bits A downto A are responsible for the burst-length. There is a choice between 4 (010) or 8 (011); but the simulation shows the pattern (100) which is definitely not defined ("Reserved"). So, what is the effective burst length? Why does the testbench deliver such false simulation results?