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Visitor
Visitor
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Registered: ‎05-22-2014

Spartan-6 DDR2 startup issue

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Hello,

I am trying to figure out a Spartan-6 DDR2 startup issue. Upon startup I am getting corrupted data through the DDR2 attached to the Spartan-6 MCB. Applying either a whole system reset or a MCB subsystem reset does not correct the issue. I am using this code succesfully in other PCB's which boot the Sp-6 from a SPI flash. This new PCB is booting the Sp-6 from a ColdFire CPU.

 

Here are some things I have discovered in testing.

 

When in this failed mode doing a Xilinx iMPACT "Verify" on the Sp-6 over JTAG fixes the issue. We know the ColdFire is properly programming the Sp-6 because it verifies through JTAG. However, even if the FPGA .bit file is different and the verify fails the issue still goes away.


When in this mode doing a Xilinx iMPACT "Program" on the Sp-6 over JTAG fixes the issue.

 

Booting the Sp-6 on this new board from a SPI flash does not have this issue. I still need to wait until the ColdFire brings the system up but then the FPGA loads from the SPI flash and the DDR2 data is good.


Sending in a Sp-6 software reset command through the ColdFire which resets the entire Sp-6 code does not fix the issue when broken and does not cause the issue when working.

 

I am guessing the JTAG "Verify" places the Sp-6 in a suspend mode and this somehow restarts the DDR2 MCB when coming out of suspend.

 

If anybody has some ideas of what to look for either in the code or testing on the bench we will really appreciate it.


Thank you,

Erik

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Visitor
Visitor
16,910 Views
Registered: ‎05-22-2014

Hi,

I think I am dealing with a Spartan-6 Startup issue. This Xilinx Answer Record covers this material.

 

http://www.xilinx.com/support/answers/42128.htm

 

So, I think the ColdFire is not sending enough CCLK's to finish the Startup sequence of the Sp-6. This is probably made worse by two things. The DONE pin only has a 10K pullup on it so the rise time is slow. Also, I had turned on the DONE pipe in the Sp-6 which delays things by one CCLK. When I placed a 110 ohm resistor on DONE my DDR2 issue went away. I would rather lean on the safe side and try a fix sending 24 CCLK's after DONE goes high so our ColdFire code is more robust.

Erik

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008
Check this ARs .

http://www.xilinx.com/support/answers/34856.html
Thanks and Regards
Balkrishan
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Visitor
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Registered: ‎05-22-2014

Balkrishan,

Thank you for the link. I read through all of these and didn't see anything that helps me. The only one that seems close is the issue about the DDR Vref changing through calibration. But for me, sending in a reset later does not fix the issue. When I send in the reset I do see the calibration test pin go low then come back high again. So I don't think that one applies here.

Thank you,

Erik

 

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Visitor
Visitor
16,911 Views
Registered: ‎05-22-2014

Hi,

I think I am dealing with a Spartan-6 Startup issue. This Xilinx Answer Record covers this material.

 

http://www.xilinx.com/support/answers/42128.htm

 

So, I think the ColdFire is not sending enough CCLK's to finish the Startup sequence of the Sp-6. This is probably made worse by two things. The DONE pin only has a 10K pullup on it so the rise time is slow. Also, I had turned on the DONE pipe in the Sp-6 which delays things by one CCLK. When I placed a 110 ohm resistor on DONE my DDR2 issue went away. I would rather lean on the safe side and try a fix sending 24 CCLK's after DONE goes high so our ColdFire code is more robust.

Erik

 

View solution in original post

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Visitor
Visitor
9,654 Views
Registered: ‎05-22-2014

Well this was exactly the issue. We added more CCLK's from the ColdFire CPU and the FPGA started properly, the DDR2 data was correct, and the system power went down by 1.3W.

Erik

 

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