Spartan 6 + DDR3, ODT not wired?

[sparkybg]

Hi,

Is it possible not to wire the ODT signal and enable the Dynamic ODT feature of DDR3 instead? From what I can see from Micron  datasheet for the part I intend to use (MT41J128M16):

Dynamic ODT Special Use Case:
When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a
special use case: the ODT ball can be wired high (via a current limiting resistor preferred)
by having RTT,nom disabled via MR1 and RTT(WR) enabled via MR2. This will allow
the ODT signal not to have to be routed yet the DRAM can provide ODT coverage during
write accesses.
When enabling this special use case, some standard ODT spec conditions may be violated:
ODT is sometimes suppose to be held low. Such ODT spec violation (ODT not
LOW) is allowed under this special use case. Most notably, if Write Leveling is used, this
would appear to be a problem since RTT(WR) can not be used (should be disabled) and
RTT(NOM) should be used.

Spartan 6 MCB does not use Write Leveling, so if I understand it correctly, there should not be a problem. Am I wrong?

[balkris]

check these links
https://www.xilinx.com/support/answers/40778.html
https://www.xilinx.com/support/answers/40779.html
https://www.xilinx.com/support/answers/38623.html
https://www.xilinx.com/support/documentation/user_guides/ug388.pdf

[sparkybg]

I've already checked these documents (except one of the answers), but Dynamic ODT is mentioned only once in UG388 as a paramater, and nothing more. From all the documents from Xlilinx, Micron, and several others I cannot see a problem, but my knowledge far from perfect, and my experience is close to nothing. That's why I am asking if someone can confirm it works or not.

[watari]

Hi sparkybg

First of all, at most, the limitation of Spatran6's MCB is DDR3-800.
In this case, you don't need to consider write leveling and read leveling to connect between Spartan6 and DRAM by fly-by topology. Because of frequency is low.

Also, you don't need to consider dynamic ODT when you don't have stub. Because of the purpose of it is to prevent reflected wave.

In other words, if you use hardwired MCB logic on Spartan6, you don't need to consider dynamic ODT.

[Note]

Of cause you need to pay attention signal integrity and condition of VREF.

Thank you.

Best regards,

[sparkybg]

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@watari wrote:

...Also, you don't need to consider dynamic ODT when you don't have stub. Because of the purpose of it is to prevent reflected wave...

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Hi warari,

Yes, I know what Dynamic ODT's primary use is. My question is if somebody can confirm that this exact scenario works on Spartan 6 + DDR3. The quote is from Micron's (ISSI and Alliance Memory also has it) datasheet:

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@Micron wrote:

Dynamic ODT Special Use Case:
When DDR3 devices are architect as a single rank memory array, dynamic ODT offers a
special use case: the ODT ball can be wired high (via a current limiting resistor preferred)
by having RTT,nom disabled via MR1 and RTT(WR) enabled via MR2. This will allow
the ODT signal not to have to be routed yet the DRAM can provide ODT coverage during
write accesses.

---

 I am considering this scenario because wiring ODT signal is a bit problematic on the 4 layer board I am designing right now. When used like this, the "normal" ODT is disabled using MR1 register, and only Dynamic ODT is enabled using MR2 register. The Spartan 6's MCB has C_MEM_DDR3_DYN_WRT_ODT parameter for enable dynamic ODT when needed.