cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
11,931 Views
Registered: ‎04-03-2008

Spartan-6 DDR3 read error in ISE 14.7 (but not in 12.4)

Hello!

We've used MIG v3.61 from ISE 12.4 to generate memory controller core for custom board with xc6slx25t-fgg484-2 and MT41J128M8XX-15E DDR3 memory. DDR3 is connected to MCB3. Power supply for DDR3 termination is similar to SP605 schematic, based on TPS51200 DDR Termination Regulator.

After upgrading to ISE 14.7 we've got DDR3 non-persistent read errors. This errors occurs at different addresses with the same data, written to the memory. First data in each following row is read from DDR3 value, second data - expected value (MCB port is configured for 32-bit width, but test is accomplished through uC with 16-bit data bus):

Data mismatch @006c659c : 63cd, 63ce
Data mismatch @006c659e : 63cd, 63cf
Data mismatch @0076ba54 : ba2c, ba2a
Data mismatch @0076ba56 : ba2c, ba2b
Data mismatch @0076ba58 : ba2e, ba2c
Data mismatch @0076ba5a : ba2f, ba2d
Data mismatch @001095ec : 93f8, 93f6
Data mismatch @001095ee : 93f8, 93f7
Data mismatch @001095f0 : 93fa, 93f8
Data mismatch @001095f2 : 93fb, 93f9
Data mismatch @001dd14c : d0a8, d0a6
Data mismatch @001dd14e : d0a8, d0a7
Data mismatch @001dd150 : d0aa, d0a8
Data mismatch @001dd152 : d0ab, d0a9
Data mismatch @005be9bc : e8e0, e8de
Data mismatch @005be9be : e8e0, e8df
Data mismatch @005be9c0 : e8e2, e8e0
Data mismatch @005be9c2 : e8e3, e8e1
Data mismatch @0056a83a : a71c, a71d

If we use ncd produced by ISE 14.7 to generate bit-file with bitgen from ISE 12.4 we always get a working firmware without any read error in test. But if we use bitgen from ISE 14.7 with the same switches as for bitgen from ISE 12.4 we always get read errors in test. Moreover, I've copied Xilinx/12.4/ISE_DS/ISE/spartan6/data/spartan6.bfd to Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6.bfd and tried to generate bit-file with ISE 14.7 bitgen. Resulting firmware successfully performed read test as produced by ISE 12.4 one.

 

What could this mean? Is there some MCB parameters error, which doesn't lead to error in 12.4, but generate read failures in 14.7?

0 Kudos
5 Replies
Highlighted
Visitor
Visitor
11,878 Views
Registered: ‎04-03-2008

We tried to test MIG example design with debug enabled on our board (with adapted frequency source and RZQ/ZIO pins placement). It works perfectly with original constraints file. So this is not PCB/PDN design problem. Further investigation shows, that the problem was in our constraints file, which enables POST_CRC configuration parameter:

CONFIG POST_CRC = ENABLE;
CONFIG POST_CRC_INIT_FLAG = ENABLE;
CONFIG POST_CRC_ACTION = CONTINUE;
CONFIG POST_CRC_FREQ = 4;

There is AR# 52716, which describes one possible problem with CONFIG POST_CRC resulting in noise on PDN Vccint network. I think, that such noise could also break MCB operation, cause it uses relatively high operation frequency (667 MHz).

 

To check this hypothesis we add CONFIG POST_CRC = ENABLE to MIG example design and we saw a lot of read errors. If we set CONFIG POST_CRC = DISABLE; in UCF-file for ISE 14.7, then read errors totally disappear in our project and in MIG example design.

 

So, something is wrong with POST_CRC = ENABLE with ISE 14.7 on 25LXT.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
11,869 Views
Registered: ‎11-28-2007

Hi,

 

Noise on VCCint is not good!Although this seems like a known issue, can you confirm that you have sufficient decoupling capacitors on your board?

(see UG393)

If you have sufficient, can you add more to test and see if it mitigates the noise?

 

Do you absolutely need the POST_CRC?

 

 

Best regards

Dries

--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.
0 Kudos
Highlighted
Visitor
Visitor
11,864 Views
Registered: ‎04-03-2008

Hi!


 

Noise on VCCint is not good!Although this seems like a known issue, can you confirm that you have sufficient decoupling capacitors on your board?

(see UG393)

If you have sufficient, can you add more to test and see if it mitigates the noise?


There are sufficient decoupling capacitors. We copied decoupling from SP605 board and checked this using UG393. Moreover latest test firmware (MIG example design) uses only small part of device and has small current consumption on Vccint. But despite of this there are read errors with POST_CRC.


Do you absolutely need the POST_CRC?

The answer is no. But this feature is declared to work and there is no errata regarding to it. And I know about SEM IP core.

 

PS: We've checked our MIG example design at another two similar boards with 45LXT and 75LXT with the same DDR3 memory chip, proper power decoupling and POST_CRC = ENABLED - no were errors detected. It seems that only 25LXT is subject to produce errors with POST_CRC enabled.

0 Kudos
Highlighted
Visitor
Visitor
11,863 Views
Registered: ‎04-03-2008

Update: but I can't clearly understand why spartan6.bfd from ISE 12.4 solves such issue with MCB and POST_CRC. Firmware binary file shows minimal differences, but I can't found any documentations to find out their meanings.
0 Kudos
Highlighted
Visitor
Visitor
11,859 Views
Registered: ‎04-03-2008

You can see binary firmwares differencies in attached file.

sp6_top.bin.12.4bfd.txt - hex dump of firmware produced by ISE 14.7 with spartan6.bfd from ISE 12.4.

sp6_top.bin.14.7bfd.txt - hex dump of firmware produced by ISE 14.7 with original spartan6.bfd.

 

I hope this could help to find out root of errors.

0 Kudos