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Visitor
Visitor
616 Views
Registered: ‎12-21-2017

Spartan 6 MIG Interface Cmd not getting written

Hi,

We are facing an issue with respect to Simulating the MIG design for a Spartan 6 FPGA.

We are able to write data into the write FIFO of the MCB and the c3_p0_write_count is increasing.

But when we are sending the command to Command FIFO the c3_p0_cmd_empty signal goes low, but writing to memory is not happening.

Attaching the Simulation screenshot.

 

Thanks,

Anup Chacko

 

DDR_Signals.PNG
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4 Replies
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Visitor
Visitor
563 Views
Registered: ‎12-21-2017

Can anybody give a hint what is missing in this.??

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Xilinx Employee
Xilinx Employee
554 Views
Registered: ‎06-30-2010

Is this simulation coming from teh example design?

 

Have you tried on Hardware? Does teh interface work there. Wondering if this is a simulation issue instead of a functional one.

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Visitor
Visitor
530 Views
Registered: ‎12-21-2017

It is working in the Hardware.

But we need the simulation to be done for the verification environment.

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Xilinx Employee
Xilinx Employee
519 Views
Registered: ‎06-30-2010

I understand that but we need to establish if this is a simulation or functional issue, if you have HW i would recommend trying the design on it so we can understand where the failure lies.

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