Spartan 7 MIG support for LPDDR devices

[bivin]

Hi

Does Spartan 7 (XC7S6-1CPGA196I ) has MIG support for LPDDR3/LPDDR2 memory?

[avcon_lee]

@bivin

LPDDR2 is supported, but it does not seem to support LPDDR3.

[nmanitri]

Hello @bivin,

Spartan-7(XC7s6-1CPGA196I) has MIG Support for LPDDR2 memory.

For more infromation please follow UG586.

Regards,

Naveen

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[bivin]

Hi

I'm using MIG 4.1, in that LPDDR2 option is not there while selecting controller type, please clarify. 

Also in latest vivado there is voltage standard of mobile_ddr, is there any guidelines for device selection for the same. 

[ryana]

Hello @bivin,

In order to select the LPDDR2 interface option for the 7-Series MIG you cannot use the AXI interface option.  If the AXI interface is enabled on the first page of the MIG configuration GUI then you will not be able to select the LPDDR2 option on the Memory Selection page.

Also for checking device capabilities like external memory interface support you should always check with the device data sheet.  In this case reference DS189 for Spartan-7 devices and you'll see the MIG memory support table which also states the maximum data rate depending on your device speed grade, voltage, and if there are any package limitations:

Here's a link to the latest version of DS189:
http://www.xilinx.com/support/documentation/data_sheets/ds189-spartan-7-data-sheet.pdf

[bivin]

Hi

I'm not using AXI interface option, also this option is inactive (not able to select). Even if it is not selected the LPDDR option is not appearing in controller type selection page. Please suggest a solution.

[ryana]

Hello @bivin,

Using Vivado 2018.2, targeting the Spartan-7 device you specified, and using Verilog as the project's Target Language I'm able to select the LPDDR2 controller option:

If you have the Project's Target Language set to VHDL then you won't have the ability to select the LPDDR2 controller.

[bivin]

I'm using Vhdl as the project's Target Language, so how can i implement the same? Why Project language difference results in an option to disappear ?

[ryana]

Hello @bivin,

It was a marketing decision to only generate the LPDDR2 IP as Verilog but Vivado does support mixed language designs.  You need to instantiate the IP as VHDL in the top level of the design along with the port assignments but the IP itself can remain Verilog.

[bivin]

Hi @ryana

You mentioned "You need to instantiate the IP as VHDL in the top level of the design along with the port assignments but the IP itself can remain Verilog.". How the same can be done, since i'm using target language as VHDL and simulation language as MIXED , i'm still not able to see LPDDR2 option in vivado.

[ryana]

Hello @bivin,

Generate the IP with Vivado set to Verilog and package it.  Then import the packaged IP in to your VHDL project.