08-25-2011 11:44 PM
Hello, we are working in Mexico with UAV technologie in Hydra Technologies de México company, and we are using the MIG 3.61 module for a 32m16 DDR memory, we are using a Spartan3E-1200k-X320(-4) FPGA, we use a tarjet that have the DDR conected to the BANK1 of the FPGA, we use a clock of 125Mhz in the MIG and the crystal of the target is of 133Mhz. The tarjet have connected the CKE (Clock Enable) signal to a PULLDOWN and to the bank 2.
We implement the code in the target, but we are surprised when we saw that it do not initialize the DDR. We Developed a module that initialize the DDR and write a data to it. We merge and implement the code with other MIG and in a Spartan3E-500k-X320(-4) when we saw that in the Spartan3E-1200k-X320(-4) FPGA do not initialize the DDR. The Spartan3E-500k-X320(-4) have a 32m16 DDR memory too, we change the net file for that target and we ganarate a new xilinx project for those targets, we test the code and in that target the code runs correctly, the DDR initialize correctly and the data is writen correctly.
When we saw that, we output the RST_180_TB signal in a led to saw if the target put that signal into zero state, but we surprised when we saw that the signal in the Spartan3E-1200k-X320(-4) FPGA is allways in rising edge state. What are the possible reazons that make the DDR never put that signal into zero state? It can be a constrain that we have to put in the net file for the CKE (Clock Enable) because it is connected to a PULLDOWN and to a BANK?.
Where can we find the net file of the MicroBlaze to saw the constrains that it use for the DDR control?
08-26-2011 07:32 AM