Speeding up simulation of DDR3 RAM in Vivado.

[mwayne_aqua]

Hello,

I am simulating a Kintex 7 FPGA with DDR3 RAM and a MIG interface. When I simulate either my design or the example design, I notice that it takes quite a long time.

I looked through the included Micron ddr3_model.sv file and on line 92-94 it says 

// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps

However, in example_top_tb.v (the top level file) the timescale is set to 1ps/100fs, and when I run Vivado simulator I get the message 'Time resolution is 1 fs'.

I therefore thought that I needed to change the simulator time resolution and under xsim.elaborate.xelab.more_options added the commands

-timescale 1ps/1ps -override_timeunit -override_timeprecision

Now this changes the Vivado tcl console to say 'Time resolution is 1 ps', but the simulation takes the exact same amount of time.

Am I doing something wrong here when trying to set the simulator resolution, or is this just how slow simulating the memory is.

Thank you.

[kren · Accepted solution]

No, but it didn't help to shorten the simulation time. For DDR3 simulation, it takes some time for inherent PHASER initialization that cannot be skipped.