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mt-user-2019
Adventurer
Adventurer
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Registered: ‎07-29-2019

True dual port PS-BRAM-PL with different ratio

Hello everyone,

My question concern True dual port Bram with different ratio with same clock .

PS <-> BRAM Port A

PS will access the port A with 32 bits width.

I was thinking to use Axi bram ctrl  and manualy link addr, clk, wrdata ...

PL <-> BRAM Port B

PS will access the port B with 16 bits width.

 

What I think IS correct :

To address a 32bits memory width I have to increment the address by 4. Address_0  : 0  /  Address_1  : 4 / Address_2  : 8  /  Address_3  : 12  / Address_4  : 16 ...

To address a 16 bits memory width I have to increment the address by 2. Address_0  : 0  /  Address_1  : 2 / Address_2  : 4  /  Address_3  : 6  / Address_4  : 8 ...

A memory (width  x depth)  32 x 1024 means that I have 256 words of 32 bits available.

There is no possible way to have a true dual port bram using 'Bram controller' mode  with different width on Port A and port B.

If I use Ps <-> axi_bram <-> Bram (bram controller mode with 32 bits width) I can not add some logic to modify the address that PS is using.

 

Thanks in advance if you see something that can Help me.

 

MT
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3 Replies
mt-user-2019
Adventurer
Adventurer
403 Views
Registered: ‎07-29-2019

is those 2 pictures are equivalent (behavior and performances) ?

1) link using the 'port' 

bram1.jpg

2) link using signals

bram2.jpg

Again thanks in advance

M

 

REPLY to myself : You can mixte (1) and (2), it seems to work

MT
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mt-user-2019
Adventurer
Adventurer
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Registered: ‎07-29-2019

On vivado, for a BRAM

read width : ... bits 

read Depth : ... words with the length of the width 

Mem Size : ...  bytes (8 bits)

 

ex :

Width : 64 bits  

Depth : 1024 'lines' of 64 bits each

Size : 8192 bytes

So you can do  ( 64 bits  * 1024 words ) /8 = 8192 bytes

MT
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mt-user-2019
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Adventurer
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Registered: ‎07-29-2019

Hi,

I did not succed to use Bram with different ratio (port A 32biits width and port B 16 bits width)  SO I use the Write enable BUS on port B .. 

MT
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