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Adventurer
Adventurer
345 Views
Registered: ‎01-20-2017

Two bank memory controller w/ DCI cascade - which bank should be master?

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We are developing a custom board: Kintex-7 FPGA (p/n xc7k160t-ffg676) interfacing with a single DDR3 memory component (Micron P/N MT41K256M16TW-107:P).  The memory signals in play only require pins from two of the HP banks (Banks 33 & 34). DCI cascade is enabled as part of the MIG.  My question is which of the two banks should I set as the 'master' in the DCI cascade scheme (None of the VRP/VRN pins are in use in either bank).  I presume I should use the bank with the address/control signals (this is Bank 34 in my case), using the following line in my .xdc constraint file:

set_property DCI_CASCADE {33} [get_iobanks 34]

However, I was wondering if there is any restriction on which bank I use to connect my precision resistors to VRP/VRN?

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Xilinx Employee
Xilinx Employee
317 Views
Registered: ‎08-21-2007

回复: Two bank memory controller w/ DCI cascade - which bank should be master?

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Either Bank 33 or 34 can be the DCI master.

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Xilinx Employee
Xilinx Employee
318 Views
Registered: ‎08-21-2007

回复: Two bank memory controller w/ DCI cascade - which bank should be master?

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Either Bank 33 or 34 can be the DCI master.

View solution in original post

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