03-22-2018 03:40 AM - edited 03-22-2018 03:46 AM
DDR3 Modules are available with burst 4 critical word first. I would like to know whether xilinx DDR3 memory controller can be customized to get burst 4 critical word first. I have gone through
https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf and found in general features that burst length must be set to 8. In customizing the core section of the above pdf gives an equation for axi data width calculation based on that also for different mc to ddr3 clock ratio (4 or 2) burst length got is 8. In DDR3 there is mode register and using mode register set command burst length could be changed but externally we could give only read and write command in ddr3 memory controller.
I would like to know whether xilinx DDR3 memory controller can be customized to get burst 4 critical word first?
03-22-2018 09:46 AM - edited 03-22-2018 09:50 AM
Unfortunately there is no way to get any other burst setting than Burst Length = 8. The controller's code is written for BL=8 only and it would take a near complete redesign of the core for it to support BC=4.
03-22-2018 08:35 PM
Thanks for your quick reply. can we customize UG586-7series-MIG DDR3 Memory controller for critical word first even though the burst length is 8?
03-22-2018 08:57 PM
OK, I think I understand your question a bit better. The interfaces to the MIG core, either the regular app_interface or the AXI shim, have no intelligence for these concepts and the read data is always returned in the order in which the read commands were accepted. The only way to get something like this is to design a complete custom controller.