I have used the Zynq UltraScale+ MPSoC to realize the Processing System and XDMA Bridge to PCI Express to implement PCIe.
I put a DDR4 SDRAM in the block design which is the DDR4_PL and I would like to allocate 2GB of memory to it. But I see in the Address Editor tab, that the maximum allowed memory cannot go beyond 512MB in the best case. Please see the attached photo of Address Editor. As you see, this DDR4_PL is ONLY seen by PCIe.
Can anoyonehelp me to overcome this problem and extend the DDR4_PL memory size?
If you look in the screenshot you provided the maximum addressable space that can be assigned in M_AXI_B is 4GB and currently you have 2GB assigned for HP0_DDR_LOW, 512MB for HP0_QSPI, and 512MB for the C0_DDR4_ADDRESS_BLOCK. Overally you're using too much of your memory map for other stuff for 2GB to be avaible for the DDR4_PL.