10-10-2016 08:31 AM
I am trying to interface two Micron DDR2 SDRAMs with a Spartan - 3AN FPGA. The signals to interface both the SDRAMs are generated using the same instance of the MIG.
The interface is working fine when running only one of the DRAMs, but on running both the DRAMs even small irrelevant changes in the code and regenerating the bit file, messes up the working of the system. The behaviour is erratic.
The ucf file for MIG has some specific mapping of the slices. How can we manage this when using two instances of MIG. Is this supported on the Spartan - 3AN?
Thanks in advance for all the help!
10-11-2016 06:04 AM
Are you able to run each DRAM independently with success? Are you seeing problems when testing the MIG Example Design on both DRAMs or only when using your own design? What is the erratic failures happening (i.e. calibration failures, data errors etc.)?
10-11-2016 06:39 AM
I havent tested the DRAMs with the MIG example design.
With my design, when running one single DRAM, the output is fine (Tested with both DRAMs independently). When running both together, there are sometimes bit errors in the output of one of the DRAMs. The bit errors seem periodic.
Also could you please tell me how I can check if there are any calibration failures?