03-04-2019 11:14 PM
I am using Vivado 2018.2 & ZCU102 board.
I have generated MIG DDR4 design using 625 MHz as Memory clock & 125 MHz as Reference clock.
I want to use CLK_125 of SI5341B Clock Generator. Since this is in HD bank, I need to have a BUFGCE in between IBUFDS & MMCM of MIG. So I choose NO Buffer as reference clock option in MIG.
I use the example design & change the xdc wrt. differential clock input pins LOC & IOSTANDARD configuration.
create_clock -period 8.000 [get_ports "c0_sys_clk_p"] #CLK_125 125 MHz U69 SI5341B set_property PACKAGE_PIN F21 [get_ports "c0_sys_clk_n"] set_property IOSTANDARD LVDS_25 [get_ports "c0_sys_clk_n"] set_property PACKAGE_PIN G21 [get_ports "c0_sys_clk_p"] set_property IOSTANDARD LVDS_25 [get_ports "c0_sys_clk_p"
When I try to implement, it generates error in opt_design
[Mig 66-99] Memory Core Error - [u_ddr4_2] System Clock ports must be assigned to the same column of I/O Banks as the memory interface. System Clock ports are assigned to the column 0 while the memory interface is assigned to the column 1.
What should I do to remove this error? Basically, I want to have DDR4 mem clock as 625 MHz, so which clock source should I rather use if CLK_125 is not allowed.
03-05-2019 07:49 AM
On the ZCU102, we reocmmend using the Silicon Labs SI570BAB001614DG. If you Drag/Drop a "DDR4 SDRAM" block from the "board" tab to the IPI Canvas, we will automatically pinout the dram for you. Then you can Drag/Drop a "User Programmible Differntial Clock" from the "board" tab to the IPI Canvas, IPI is aware to connect this default 300MHz clock to DDR4. This is how the DDR4 IP was qulaified on the ZCU102. And lastly you can Drag/Drop a "FPGA Reset" block from the "board" tab to the IPI Canvas and we will automatically connect a reset to DDR4.
Doing this flow will let you skip pinning out the DDR4 IP completely with the ZCU102.
Clock Pinout for reference:
set_property PACKAGE_PIN AL7 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64
set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_N"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64
set_property PACKAGE_PIN AL8 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64
set_property IOSTANDARD DIFF_SSTL12 [get_ports "USER_SI570_P"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64
Reset Pinout for reference:
set_property PACKAGE_PIN AM13 [get_ports "CPU_RESET"] ;# Bank 44 VCCO - VCC3V3 - IO_L4N_AD8N_44
set_property IOSTANDARD LVCMOS33 [get_ports "CPU_RESET"] ;# Bank 44 VCCO - VCC3V3 - IO_L4N_AD8N_44
03-05-2019 09:06 PM
@corybThanks for the reply. I had read & followed the xtp432 ZCU102 MIG Design creation. I have read that DDR4 SDRAM component memory provided with ZCU102 can have a mem clock freq from 625 MHz to 1333 MHz. So, I want to use the minimum freq of 625 MHz. But Si570 user clock of 300 MHz can't really generate mem clock of 625 MHz. Hence, I need a clock source that can generate 625 MHz. I can use either 125 MHz or 156.25 MHz as reference clock for MIG.
From ZCU102 User Guide (ug1182), I see that there is Si570 MGT (156.25 MHz) or CLK125 from Si5341B (125 MHz) that can be used. But as mentioned in the OP, I can't seem to use CLK_125 MHz.
So, since DDR4 MIG allows 625 MHz mem clock & I intent to use it, which is the reference clock source best recommended by Xilinx for this particular case.