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Adventurer
Adventurer
436 Views
Registered: ‎10-13-2016

Using MIG core on KC705

hi, 

 

I am using KC705(Kintex-7) evaluation board fand wanted to data into DDR3 SDRAM using MIG

i followed the following steps to write data into DDR3

1. I generated the app_addr[27 dowto 0] with all bits zeros.

2. I have generated a data input for app_wdf_data[511 downto 0].

3. I have set  app_cmd= "000"  for writing.

4. made app_en= '1' after address and cmd were given

5. i ran the simulation but app_rdy output signal coming from  IP core is
   always zero.

   only when the app_rdy is 1 the write to DDR3 will progress.

i am not able to understand cause for this behaviour.

can you please let me know what the issue is?

The ddr3_dq which is data bus is always showing high impedance state.





component mig_7series_0
  port (
      ddr3_dq       : inout std_logic_vector(63 downto 0);
      ddr3_dqs_p    : inout std_logic_vector(7 downto 0);
      ddr3_dqs_n    : inout std_logic_vector(7 downto 0);

      ddr3_addr     : out   std_logic_vector(13 downto 0);
      ddr3_ba       : out   std_logic_vector(2 downto 0);
      ddr3_ras_n    : out   std_logic;
      ddr3_cas_n    : out   std_logic;
      ddr3_we_n     : out   std_logic;
      ddr3_reset_n  : out   std_logic;
      ddr3_ck_p     : out   std_logic_vector(0 downto 0);
      ddr3_ck_n     : out   std_logic_vector(0 downto 0);
      ddr3_cke      : out   std_logic_vector(0 downto 0);
          ddr3_cs_n     : out   std_logic_vector(0 downto 0);
      ddr3_dm       : out   std_logic_vector(7 downto 0);
      ddr3_odt      : out   std_logic_vector(0 downto 0);
      app_addr                  : in    std_logic_vector(27 downto 0);
      app_cmd                   : in    std_logic_vector(2 downto 0);
      app_en                    : in    std_logic;
      app_wdf_data              : in    std_logic_vector(511 downto 0);
      app_wdf_end               : in    std_logic;
      app_wdf_mask              : in    std_logic_vector(63 downto 0);
      app_wdf_wren              : in    std_logic;
      app_rd_data               : out   std_logic_vector(511 downto 0);
      app_rd_data_end           : out   std_logic;
      app_rd_data_valid         : out   std_logic;
      app_rdy                   : out   std_logic;
      app_wdf_rdy               : out   std_logic;
      app_sr_req                : in    std_logic;
      app_ref_req               : in    std_logic;
      app_zq_req                : in    std_logic;
      app_sr_active             : out   std_logic;
      app_ref_ack               : out   std_logic;
      app_zq_ack                : out   std_logic;
      ui_clk                    : out   std_logic;
      ui_clk_sync_rst           : out   std_logic;
      init_calib_complete       : out   std_logic;
      -- System Clock Ports
      sys_clk_p                 : in    std_logic;
      sys_clk_n                 : in    std_logic;
    sys_rst                     : in    std_logic
  );
end component mig_7series_0;

Thanks and Regards
Gaonkar

 

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5 Replies
Adventurer
Adventurer
385 Views
Registered: ‎10-13-2016

Re: Using MIG core on KC705

below is the top module code

anyone can let me know what is wrong in this code.

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Xilinx Employee
Xilinx Employee
378 Views
Registered: ‎08-21-2007

Re: Using MIG core on KC705

Did you wait until init_calib_complete= 1?

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Adventurer
Adventurer
362 Views
Registered: ‎10-13-2016

Re: Using MIG core on KC705

ya i ran the simulation for more than 100us but still the init_calib_complete never become 1.

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Xilinx Employee
Xilinx Employee
354 Views
Registered: ‎08-21-2007

Re: Using MIG core on KC705

For MIG design, you should wait for init_calib_complete=1 and then start write/read operation at user interface. Are you using the MIG IP example design? If not, please have a try with it first and then compare your testbench with it.

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Adventurer
Adventurer
344 Views
Registered: ‎10-13-2016

Re: Using MIG core on KC705

hi i tried the example design and i am not getting init_calib_complete = 1. Is there anything wrong in my code ?

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