Using double rank DDR3 memory in vc707

[meta1360]

Dear All,

I have a problem when I want to select pins of FPGA in GUI of MIG; the problem is that I chose a double rank SODIMM in its option in second page of MIG's GUI and when I wanted to select the appropriate pins for memory accoridng to VC 707 documents I chose G18, H19, and F19, G19 for clk0_N, clk0_p,  Clk1_n, and clk1_P respectively but I encountered this problem 

All Write Clock pairs should be allocated in same byte group. ddr3_ck_p[1], ddr3_ck_n[1] signals are allocated in FPGA Byte-T1 of Bank-33 whereas ddr3_ck_p[0], ddr3_ck_n[0] signals are allocated in FPGA Byte-T2 of Bank-33.

it is not possible to change T1 and T2 because it is up to the board I am using and its design it is not changable  

I also saw another thread having this problem but wothout answer

http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/MIG-error-with-KC705/td-p/328819

your prompt reply would be really appreciated 

Meysam

[vsrunga]

HI,

VC707 is a old Dev board.

It is designed even before MIG has not added Dual rank support.

So it won't satisfy dual rank rules, if you want you may generate MIG and modify the xdc and RTL parameters mnaually and try to run the memory at lower frequencies.

For knowledge on different memory related parameters please refer UG586 ADDR_MAP, CK_MAP, ODT_MAP etc.,

Regards,

Vanitha

[meta1360]

thank you so much I am really stuck at that. 

I did the same, meaning in GUI I chose something for clk1_n and clk1_p and then changed the XDC file to real ports. but after implementation I got this error

[Route 35-54] Net: MIGBlaze_i/mig_7series_0/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clk is not completely routed.

and one net is left untouted. If you have any idea where I did something wrong I really appreciate it

Meysam
 

[meta1360]

but according to http://www.xilinx.com/support/answers/60166.html, if we modify XDC file we must regenerate the MIG and if we do that, that XDC file would be overwritten, but without doing that, we might get this error. What can I do ?

thanks,

Meysam

[vsrunga]

Hi,

The answer record is correct, but as said earlier defult configuration of the eval board do not support dual rank SODIMM, board is not designed for it, hence if you need to do the modifications manually and test it.

It is an achievable task but needs understanding of the concepts and time to evaluate them.

Regards,

Vanitha

[meta1360]

Actually, I decided to choose two fake ports just to be able to move forward in GUI of MIG and then just work with one rank of SODIMM but the only option I had was E18/E19 because I had to assign two pairs of pin from the same number of byte (eitherT1 and T1 or T2 and T2) and if I chose both T2 there is just one pin left to assign while I need two pins and if I chose both T1 there are just two pins left (E18/E19) but another problem raised; these two pins (E18 and E19) were selected as input clock (200 MHZ) for my system. Then, I made decision to change the input clock and thankfully there are three options as source of clock on VC 707

1- system clock which produces 200 MHZ clock connected to E18/E19

2- Programmable user clock ranging from 80 MHZ to 800 MHZ 

3- external clock 

option 1 is not possible for me because of what is mentioned above but second and third options are not possible as well because the pins of FPGA these sources of clock are connected to are in banks 14, 113, 114, and 13 none of which are allowed to be connected to SYS_clk of Memory controller in its GUI.

since I was in rush to fix it I also sent another thread talking about this problem.

thank a lot for all your help

Meysam

[vsrunga]

Hi,

As the board is already built with limited number of clock sources it  would be difficult to go with your workarounds.

MIG and VC707 does support 1GB but it is single rank!

Please go through xtp206 and generate MIG with memory options shown in page -19, you may go for similar 1GB part but it should be single rank for VC707.

http://www.xilinx.com/support/documentation/boards_and_kits/vc707/2014_2/xtp206-vc707-mig-c-2014-2.pdf

Regards,

Vanitha

[meta1360]

Yes as you said I chose a dual rank SODIMM from that list shown in Page 19 to make a dual rank memory controller but all these problems happen after that. I could not understand what you mean by choosing options of that page please explain it 

thank you so much for all your help 

Meysam

[vsrunga]

Hi,

Page 19 of XTP 206 shows Single Rank as the slected part for VC707

Regards,

Vanitha

[meta1360 · Accepted solution]

yes you are right but there is no way to use any dual rank SODIMM in this board? becasue MIG has some other options which are dual rank and when we select them everything is OK but just becasue of that problem (clocks of SODIMM should be chosen in both T1) we could not move forward. is there any way to cirumvent GUI of MIG or any other way? is there any way to use the output of programmable clock as MIG input clock?  

sorry for keeping asking question back and forth but I really need to use this SODIMM 

[vsrunga]

Hi,

Manually modifying the design might have been possible(but un tested)  if you have other clocking options on the board but

 as said earlier we do not have option to use dual rank SODIMM, this is because the board designed for single rank.

If it is custome board/other dev boards then you might be having choices for the corrent board please use single rank SODIMM