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chirag1208_1
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Registered: ‎03-21-2021

Versal LPDDR4 phy Configuration

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Hi Xilinx

 

Can anyone know how to access LPDDR4 phy independently from NOC in Vesal FPGA. i want to use my own Softcore IP for LPDDR4 so how i can access PHY independently or access Register which need in calibration of LPDDR4. I read and go through PG313 try some simple design with help of NOC IP in vivado 2020.2 but i can't access PHY directly.

Please help me out if anyone know how to use it.

 

Thanks 

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rpr
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Registered: ‎11-09-2017

Hi @chirag1208_1 

Present there is no support to access by CIPS but this is valid use case. I will share the feedback with the concerned team and I believe future tools will get added with this feature.

Regards
Pratap

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rpr
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Registered: ‎11-09-2017

Hi @chirag1208_1 

Presently there is no support for NOC LPDDR4 PHY only interface. You cannot access PHY only directly.

Regards
Pratap

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chirag1208_1
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Registered: ‎03-21-2021

Is there any way to access debug Register which is mention in PG313 topic Calibration Stage in Appx A?

I want to run time access this register. Can i access this register by CIPS with debug controller.?

Thanks for help

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rpr
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Moderator
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Registered: ‎11-09-2017

Hi @chirag1208_1 

Present there is no support to access by CIPS but this is valid use case. I will share the feedback with the concerned team and I believe future tools will get added with this feature.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.

View solution in original post

chirag1208_1
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Registered: ‎03-21-2021

Hi @rpr 

Thank you for immediate support. 

Is there any other method to access this Debug registers. let's say i want to access "Fx_CALBISC_RL_DLY_QTR" this register for PHY BISC which is first stage of calibration. so is there any way to access this register? OR any register mapping to this register so i can modified it in RTL side?

Thanks for your support.

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