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Visitor maxbaker
Visitor
9,055 Views
Registered: ‎02-06-2014

Vivado 2014.3/2014.4 inserts BUFG between PLL and Phaser for QDR-II MIG design

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Hi,

 

I'm trying to qualify Vivado 2014.3 / 2014.4 for our use and I'm running into a design that uses MIG for a QDR-II part.

  • For 2014.2 everything works great, the design is fully qualified
  • For 2014.3/2014.4 evaluations, there is no change to the RTL or flow, only the tool version. Both versions behave the same.

The problem I'm seeing is in the clock routing between the PLL and the phasers for the MIG design.  

- For 2014.2 this path uses the CMT Dedicated Route = BACKBONE path.

- For 2014.3 this path automatically inserts a BUFG and does not the BACKBONE path, which causes the design to run out of local clock tree and fail to route

 

[report_clock_utilization]

2014.2

1. Clock Primitive Utilization
------------------------------

+-------+------+-----------+-----------+
| Type  | Used | Available | Num Fixed |
+-------+------+-----------+-----------+
| BUFG  |    8 |        32 |         0 |
| BUFH  |    0 |       120 |         0 |
| BUFIO |    0 |        32 |         0 |
| MMCM  |    4 |         8 |         4 |
| PLL   |    1 |         8 |         1 |
| BUFR  |    0 |        32 |         0 |
| BUFMR |    1 |        16 |         0 |
+-------+------+-----------+-----------+
7. List of Nets using CMT BACKBONE routing
------------------------------------------

+-------+---------------+-----------------------------------------------+------------+
| Index | Net Name      | Sample Node Name                              | CMT Column |
+-------+---------------+-----------------------------------------------+------------+
|     1 | freq_refclk   | CMT_TOP_L_UPPER_T_X181Y96/PLL_CLK_FREQ_BB0_NS |    Right   |
|     2 | clk_mem       | CMT_TOP_L_UPPER_T_X181Y96/PLL_CLK_FREQ_BB1_NS |    Right   |
|     3 | sync_pulse    | CMT_TOP_L_UPPER_T_X181Y96/PLL_CLK_FREQ_BB2_NS |    Right   |
|     4 | Clk/cmdClkPLL | CMT_TOP_L_UPPER_T_X181Y44/PLL_CLK_FREQ_BB2_NS |    Right   |
|     5 | expClkIn      | CMT_TOP_L_UPPER_T_X181Y44/PLL_CLK_FREQ_BB3_NS |    Right   |
+-------+---------------+-----------------------------------------------+------------+

 

 

2014.3

1. Clock Primitive Utilization
------------------------------

+-------+------+-----------+-----------+
| Type  | Used | Available | Num Fixed |
+-------+------+-----------+-----------+
| BUFG  |   10 |        32 |         0 |
| BUFH  |    0 |       120 |         0 |
| BUFIO |    0 |        32 |         0 |
| MMCM  |    4 |         8 |         4 |
| PLL   |    1 |         8 |         1 |
| BUFR  |    0 |        32 |         0 |
| BUFMR |    1 |        16 |         0 |
+-------+------+-----------+-----------+

 

7. List of Nets using CMT BACKBONE routing
------------------------------------------

+-------+---------------+-----------------------------------------------+------------+
| Index | Net Name      | Sample Node Name                              | CMT Column |
+-------+---------------+-----------------------------------------------+------------+
|     1 | sync_pulse    | CMT_TOP_L_UPPER_T_X181Y96/PLL_CLK_FREQ_BB0_NS |    Right   |
|     2 | Clk/cmdClkPLL | CMT_TOP_L_UPPER_T_X181Y96/PLL_CLK_FREQ_BB3_NS |    Right   |
|     3 | expClkIn      | CMT_TOP_L_UPPER_T_X181Y44/PLL_CLK_FREQ_BB1_NS |    Right   |
+-------+---------------+-----------------------------------------------+------------+

 

 

I've tried adding the following constraints:

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets freq_refclk]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mem]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sync_pulse]

 

But after I spit out the flat XDC at the end of the run the BUFG seems to be applied before these are taken:

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_netsfreq_refclk_BUFG]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_mem_BUFG]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sync_pulse]

 

 

Anyone have any idea what changed w/ 2014.3 and how to fix this?

 

Thanks,

-m

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Visitor maxbaker
Visitor
14,499 Views
Registered: ‎02-06-2014

Re: Vivado 2014.3/2014.4 inserts BUFG between PLL and Phaser for QDR-II MIG design

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Found an answer finally : http://www.xilinx.com/support/answers/63165.html

 

Of the solutions there :

1. don't do a retarget in opt_design -- this breaks chipsscope

2. This works, horray!  Now I can get on to getting chipscope working and fix my real problems.

set_param logicopt.enableBUFGinsertCLK 0

3. add the (* dont_touch = "TRUE" *) -- this doesn't work.

In the presence of (* buffer_type = "none" *) the dont_touch doesn't take

With the dont_touch I see this, which is a fail:

 

 

...
INFO: [Synth 8-4472] Detected and applied attribute dont_touch = true [/path/to/file.sv:207]
...
WARNING: [Synth 8-5396] Clock pin MEMREFCLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/path/to/user_design/rtl/phy/mig_7series_v2_1_qdr_rld_phy_4lanes.v:768]
...
INFO: [Opt 31-194] Inserted BUFG freq_refclk_BUFG_inst to drive 8 load(s) on clock net freq_refclk
INFO: [Opt 31-194] Inserted BUFG clk_mem_BUFG_inst to drive 7 load(s) on clock net clk_mem
INFO: [Opt 31-194] Inserted BUFG sync_pulse_BUFG_inst to drive 7 load(s) on clock net sync_pulse
INFO: [Opt 31-193] Inserted 3 BUFG(s) on clock nets

 

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6 Replies
Visitor maxbaker
Visitor
9,050 Views
Registered: ‎02-06-2014

Re: Vivado 2014.3/2014.4 inserts BUFG between PLL and Phaser for QDR-II MIG design

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This is on a Kintex-7 160t Part by-the-way.
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Visitor maxbaker
Visitor
9,040 Views
Registered: ‎02-06-2014

Re: Vivado 2014.3/2014.4 inserts BUFG between PLL and Phaser for QDR-II MIG design

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OK I tried adding this into the RTL, and this is accepted by synthesis. 

(* buffer_type = "none" *) wire freq_refclk;
(* buffer_type = "none" *) wire clk_mem;

 

However, it turns out the BUFG is being added by Phase 1 of [opt_design]

Command: opt_design -verbose -directive Default 
...
Phase 1 Retarget
...
INFO: [Opt 31-194] Inserted BUFG freq_refclk_BUFG_inst to drive 8 load(s) on clock net freq_refclk
INFO: [Opt 31-194] Inserted BUFG clk_mem_BUFG_inst to drive 7 load(s) on clock net clk_mem
INFO: [Opt 31-193] Inserted 2 BUFG(s) on clock nets
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 2021682d4

 

Anyone know how to make [opt_design] not do this?

 

Thanks,

-m

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Xilinx Employee
Xilinx Employee
9,025 Views
Registered: ‎09-20-2012

Re: Vivado 2014.3/2014.4 inserts BUFG between PLL and Phaser for QDR-II MIG design

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Hi,

Did you apply the attribute on correct net? Open implemented desig and search for tool inserted bufg instances. Go to the driver net of these buffers in schematic and check if buffer_type is set or not in the net properties.

If property is applied but still bufgs are inserted then try adding dont_touch attribute on these nets.

Also check this article http://www.xilinx.com/support/answers/59654.html

Thanks,
Deepika.
Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
8,955 Views
Registered: ‎09-20-2012

Re: Vivado 2014.3/2014.4 inserts BUFG between PLL and Phaser for QDR-II MIG design

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Hi @maxbaker

Did that help?

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Visitor maxbaker
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Registered: ‎02-06-2014

Re: Vivado 2014.3/2014.4 inserts BUFG between PLL and Phaser for QDR-II MIG design

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No.

 

I still got the errors :

 

ERROR: [Drc 23-20] Rule violation (RTSTAT-6) Partial conflict - 2 net(s) have a partial conflict. The problem net(s) are freq_refclk_BUFG, smaClk.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

 

I never did get a fix for this problem, except to remove the -retarget option from opt_design.  This prevented the insertion of the extra BUFG

 

opt_design -propconst -sweep

This was a kludgy workaround, but livable. 

 

However, now when I try to insert an ILA for chipscope it fails.  Apparently the -retarget is required for chipscope designs

Replacing black box 'dbg_hub' with implemented instance
WARNING: [Constraints 18-1079] Register dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_
WARNING: [Constraints 18-1079] Register dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_
WARNING: [Constraints 18-1079] Register dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_
WARNING: [Constraints 18-1079] Register dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_
Parsing XDC File [/some/path/tmp/.Xil_max/Vivado-4975-cfc2.a.net/dbg_hub_CV.0/out/xsdbm.xdc] for cell 'dbg_hub/inst'
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:5.0 for cell u_ila_0_CV.
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:5.0 for cell u_ila_1_CV.
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2606.352 ; gain = 0.000 ; free physical = 59567 ; free virtual = 80601
INFO: [Drc 23-27] Running DRC with 4 threads
ERROR: [Drc 23-20] Rule violation (NDRV-1) Driverless Nets - Net u_ila_0/sl_iport0[1] is undriven.
ERROR: [Drc 23-20] Rule violation (NDRV-1) Driverless Nets - Net u_ila_1/sl_iport0[1] is undriven.
INFO: [Vivado_Tcl 4-198] DRC finished with 2 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado_Tcl 4-384] ECO checks failed. Please manually place the cells indicated.

If I re-add the -retarge to [opt_design] the above goes away, but the original bug comes back.  So in effect, I cannot use ChipScope in the presence of this Vivado 2014.4 / 2014.2 Bug. 

 

I'm downloading 2015.2 to see if it helps.

 

-m

 

 

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Visitor maxbaker
Visitor
14,500 Views
Registered: ‎02-06-2014

Re: Vivado 2014.3/2014.4 inserts BUFG between PLL and Phaser for QDR-II MIG design

Jump to solution

Found an answer finally : http://www.xilinx.com/support/answers/63165.html

 

Of the solutions there :

1. don't do a retarget in opt_design -- this breaks chipsscope

2. This works, horray!  Now I can get on to getting chipscope working and fix my real problems.

set_param logicopt.enableBUFGinsertCLK 0

3. add the (* dont_touch = "TRUE" *) -- this doesn't work.

In the presence of (* buffer_type = "none" *) the dont_touch doesn't take

With the dont_touch I see this, which is a fail:

 

 

...
INFO: [Synth 8-4472] Detected and applied attribute dont_touch = true [/path/to/file.sv:207]
...
WARNING: [Synth 8-5396] Clock pin MEMREFCLK has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net [/path/to/user_design/rtl/phy/mig_7series_v2_1_qdr_rld_phy_4lanes.v:768]
...
INFO: [Opt 31-194] Inserted BUFG freq_refclk_BUFG_inst to drive 8 load(s) on clock net freq_refclk
INFO: [Opt 31-194] Inserted BUFG clk_mem_BUFG_inst to drive 7 load(s) on clock net clk_mem
INFO: [Opt 31-194] Inserted BUFG sync_pulse_BUFG_inst to drive 7 load(s) on clock net sync_pulse
INFO: [Opt 31-193] Inserted 3 BUFG(s) on clock nets

 

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