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kencrocker
Visitor
Visitor
8,496 Views
Registered: ‎12-08-2014

Vivado 2014.4 MIG7v2.3 DDR3 simulation Odd Behaviour

Hi,

 

I am using the MIG generated sim.do script with modelsim to simulate the MIG example design.

As part of DDR3 initialisation, MIG seems to be issuing activate bank 0 row 0 followed by lots of read commands with undefined bank, col, and address (see attachment). The DDR3 model is not surprisingly returning undefined DQ.

Is this intentional behaviour as a bank and row have been opened?

It is causing problems with our DDR3 simulation model.

 

Ken

Clipboard01.jpg
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3 Replies
kencrocker
Visitor
Visitor
8,492 Views
Registered: ‎12-08-2014

This is the equivalent capture using Vivado 2014.2 MIG2.1

Clipboard02.jpg
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vsrunga
Xilinx Employee
Xilinx Employee
8,483 Views
Registered: ‎07-11-2011

Hi,

 

Even after initialization MIG takes about 50 us to complete calibration, please run the simulation for some more time and check for init_calib_complete signal and then you can start your write /read interface.

If you do not see after calibration then please get back.

You can refer UG586 for more details.

Also please make a note that MIG simulation is supported only with IP generated model, other models may/may not work and needs testbench modifications which are out of scope of support

 

Hope this helps

 

-Vanitha

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kencrocker
Visitor
Visitor
8,476 Views
Registered: ‎12-08-2014

Hi Vanitha,

 

The design I am simulating works in hardware.

The MIG example design also passes simulation.

If I 'hack' our DDR3 model to accept READ commands with undefined address/bank, then my simulation passes.

My proposition is that I should not need to 'hack' my DDR3 model as MIG v2.1 initialisation exhibited reasonable behaviour by executing READ commands with defined address/bank, and MIG v2.3 is deficient in this regard.

 

Thanks

 

Ken

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