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Adventurer
Adventurer
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Registered: ‎06-18-2016

Which of these data path architectures is the simplest for recording video?

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Hi All,

In my ZC706 application I need to store small video frames (10K pixels max) at a frame rate up to 10KHz. Streaming store/recall only, no processing of frame data is performed. Initial stream latency is not an issue. My first thought was to avoid PS memory completely and store to PL-accessible SODIMM from my PL logic with the MIG-created DDR3 memory interface hiding the DDR-specific parts. I generated the memory interface IP and started to implement a simple design around it, but I don't have the experience to know if this is really the least complex way. Here are the options I am considering:

1 - As above, with PL logic writing data to the generated memory interface (similar to the way I would write to sequential BRAM locations)
2 - Enable AXI option in memory interface IP and stream to AXI from my logic, potentially using a custom AXI master
3 - Store to PS DDR3 memory through AXI ACP/HP (TRM table 22-8 describes these as "More complex PL Master design")

Thanks for any advice,
Tom

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Adventurer
Adventurer
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Registered: ‎06-18-2016

Hi Yoichi,

Thanks for your suggestions. That's exactly what I needed. I followed your steps for creating the simple block design with just the processor and MIG. When I ran the MIG customization the option for generating the AXI interface was checked and grayed out, so I had to accept AXI. I ran the assistants in the block design and it created a few extra blocks and the processor now connects with the MIG via AXI and the AXI SMC block. The MIG is mapped into memory starting at 0x4000_0000 and the slave interface is listed as S_AXI.

However, after programming the device when I use XSCT terminal to attempt to read memory in that range, it says the memory is blocked and I think it also said something about AXI. If I try to read with devmem under Linux on the Zynq, I also cannot read which is what I expected.

My questions are:
1 - In order to read/write memory directly using the terminal do I need to customize MIG to *not* use the AXI interface? And if so how do I get MIG to let me uncheck the AXI box? (If not using AXI, I'm confused about how a MIG user interface would connect to the processor.)
2 - Since you gave some references to IP packaging docs, do I need to package the MIG-generated interface before I can use it for this initial test?
3 - After customizing MIG by double-clicking on it in the block design, and then clicking on Generate Block Design, I get the following message "[Vivado 12-3563] The Nested sub-design 'D:/Clients/NPS/rtp_box/ddr3_demo_a/ddr3_demo_a.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1.xci' can only be generated by its parent sub-design." What am I doing wrong here?

Thanks,
Tom

 

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Xilinx Employee
Xilinx Employee
442 Views
Registered: ‎11-05-2019

 

Hello @tgschneider 

 

I think, your understanding is correct.

 

If you need to access PS-DDR from PL, you need to make the custom AXI Master block, and connect to AXI HP port of PS.

The DDR contoroller IP ( generated by MIG ) has either AXI or Native I/F.

Which I/F you use depends on your experience.

 

If you have never used the ZC706 PL-DDR, I think it is necessary to create a simple design and successfully access the PL-DDR.

You can use the ZC706 Board settings that come with Vivado.

- Create a design with only PS and MiG on Block Design, and complete the bitstream generation.

- Using XSDK/XSCT terminal, use the mwr/mrd command to check that the PL-DDR can be read&write.

 

UG586 - 7Series FPGAs Memory Interface Solution User Guide

ZC706 - ZC706 Documents

UG1118 - Vivado Creating and Packaging Custom IP

UG1119 - Vivado Creating and Packaging Custom IP Tutorial

UG761 - AXI Reference Guide

 

Thanks

Yoichi

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Highlighted
Adventurer
Adventurer
389 Views
Registered: ‎06-18-2016

Hi Yoichi,

Thanks for your suggestions. That's exactly what I needed. I followed your steps for creating the simple block design with just the processor and MIG. When I ran the MIG customization the option for generating the AXI interface was checked and grayed out, so I had to accept AXI. I ran the assistants in the block design and it created a few extra blocks and the processor now connects with the MIG via AXI and the AXI SMC block. The MIG is mapped into memory starting at 0x4000_0000 and the slave interface is listed as S_AXI.

However, after programming the device when I use XSCT terminal to attempt to read memory in that range, it says the memory is blocked and I think it also said something about AXI. If I try to read with devmem under Linux on the Zynq, I also cannot read which is what I expected.

My questions are:
1 - In order to read/write memory directly using the terminal do I need to customize MIG to *not* use the AXI interface? And if so how do I get MIG to let me uncheck the AXI box? (If not using AXI, I'm confused about how a MIG user interface would connect to the processor.)
2 - Since you gave some references to IP packaging docs, do I need to package the MIG-generated interface before I can use it for this initial test?
3 - After customizing MIG by double-clicking on it in the block design, and then clicking on Generate Block Design, I get the following message "[Vivado 12-3563] The Nested sub-design 'D:/Clients/NPS/rtp_box/ddr3_demo_a/ddr3_demo_a.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_1/design_1_mig_7series_0_1.xci' can only be generated by its parent sub-design." What am I doing wrong here?

Thanks,
Tom

 

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Xilinx Employee
Xilinx Employee
349 Views
Registered: ‎11-05-2019

 

Hello @tgschneider 

We cannot access DDR from XSCT just by opening XSDK.
Before that, it is necessary to download Bitstream and set the PS settings.
After creating a helloworld application with XSDK and running it, you can access DDR by mrw/mrd command on XSCT window.
When you run the helloworld app, you can see the following sequence of commands running in the SDK.log window.

fpga
loadhw
ps7_init
ps7_post_config

 

I think that you can try by referring to these.

 

Thank you

Yoichi

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