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Explorer
Explorer
1,049 Views
Registered: ‎04-19-2016

Why AXI interface is not supported for QDR SRAMs in MIG ?

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Dear All,

 

I have three questions : 

 

*I wonder that why MIG IP does not support the AXI interface for QDR-SRAMs ? QDR -SRAM interface is not feasible for AXI ?

*How could an AXI-VDMA or Zynq (ARM) read/write data from/to an QDR SRAM ? 

*I want to use a 2GB DDR3 - SDRAM(64-bit) and a 288Mbit QDRII+ (36-bit) on the PL-side of my Zynq device on my custom-board. Is there a generic rule on which FPGA bank to use for QDR-SRAM and which FPGA bank to use for DDR3 -SDRAM on the Zynq- XC7Z045?  

 

Regards,

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1 Solution

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Moderator
Moderator
1,422 Views
Registered: ‎11-28-2016

Re: Why AXI interface is not supported for QDR SRAMs in MIG ?

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Hello @doner_t,


The reason the AXI option isn't available for QDR interfaces is because the AXI shim adds additional latency to the data flow which is contradictory when using a low latency SRAM memory like QDR.

 

As for talking AXI to the QDR I would investigate the AXI shim that's generated by IPs that support it (DDR3/DD2) and look in to modifying it for the QDR application. This is a custom solution that would have to be tested and verified by you.

 

Regarding the bank questions you'll have to look at the Zynq data sheets and see which operating frequencies are supported in the High Range and High Performance banks.  After that I would consult UG586 and make sure you can fit the interfaces in to those banks while adhering to the Pin and Bank rules.

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1 Reply
Moderator
Moderator
1,423 Views
Registered: ‎11-28-2016

Re: Why AXI interface is not supported for QDR SRAMs in MIG ?

Jump to solution

Hello @doner_t,


The reason the AXI option isn't available for QDR interfaces is because the AXI shim adds additional latency to the data flow which is contradictory when using a low latency SRAM memory like QDR.

 

As for talking AXI to the QDR I would investigate the AXI shim that's generated by IPs that support it (DDR3/DD2) and look in to modifying it for the QDR application. This is a custom solution that would have to be tested and verified by you.

 

Regarding the bank questions you'll have to look at the Zynq data sheets and see which operating frequencies are supported in the High Range and High Performance banks.  After that I would consult UG586 and make sure you can fit the interfaces in to those banks while adhering to the Pin and Bank rules.

View solution in original post