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Observer lasthorizon711
Observer
241 Views
Registered: ‎07-31-2018

Write timing for MIG 7 series with a native interface

Hi, 

I am desiging using the 7 series MIG IP and the native interface. From the data sheet for the IP it reads: "When the user logic app_en signal is asserted and the app_rdy signal is asserted from the UI, a command is accepted and written to the FIFO by the UI. The command is ignored by the UI whenever app_rdy is deasserted. The user logic needs to hold app_en High along with the valid command and address values until app_rdy is asserted as shown in Figure 1-53". The image then shows a scenario where app_en is driven high on the same clock edge as app_rdy going low, therefore app_en must be held high until app_rdy is re-asserted. However the datasheet is not clear as to what happens in the following situation: 

image.png

This time app_rdy is high when app_en is driven, but on the next rising edge of the clock app_rdy is deasserted. Has a write transaction taken place in this situation? Judging by the simulation of the data I read back from address 0x400 this did not write as expected. 

=== EDIT === 

Is there anyone from Xilinx that can help with this issue? The service request portal is very limited in terms of getting technical help it seems!

 

Thanks 

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Observer lasthorizon711
Observer
230 Views
Registered: ‎07-31-2018

Re: Write timing for MIG 7 series with a native interface

As a bit more information, the entire transaction (8 words) looks like this: 

image.png

When i read back starting at the same address then i receive data from the 4th data word from the write transaction 

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