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Scholar hbucher
Scholar
2,436 Views
Registered: ‎03-22-2016

Write transaction overflow through AXI4-full

Implemented HLS IP and connected it to DDR4 SDRAM (zcu102). 

The memory interface is defined as AXI4-full. 

I write three 32-bit numbers (mem[j] = j). The two writes go fine but the third one gets a BRESP as DECERR.

Waveform shows OVERFLOW (outstanding transaction limit per ID reached).

Is this a MIG issue or an AXI issue? Where does the limit 2 come from? Is the solution to lower the outstanding writes on HLS through a pragma directive?

Thank you.

 

 

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memerr1.PNG
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4 Replies
Xilinx Employee
Xilinx Employee
2,349 Views
Registered: ‎08-21-2007

Re: Write transaction overflow through AXI4-full

You can have a try to write less data. It is not a issue within MIG IP.

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Visitor yasing.shi
Visitor
1,924 Views
Registered: ‎08-14-2017

Re: Write transaction overflow through AXI4-full

Hi! I also have this problem when I write data to DDR using xdma axi4 interface, the write response is no error. so what's that overflow meaning and when it will happen? 

 

axi4_overflow.PNG
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Observer ronagyl_adi
Observer
1,853 Views
Registered: ‎05-11-2018

Re: Write transaction overflow through AXI4-full

This seems to be caused by an ILA parameter which is not automatically propagated from the AXI bus.

 

AXI_ILA.PNG

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Visitor hamidnaghi
Visitor
1,552 Views
Registered: ‎03-12-2018

Re: Write transaction overflow through AXI4-full

Perfect!

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