09-07-2017 06:39 AM
Implemented HLS IP and connected it to DDR4 SDRAM (zcu102).
The memory interface is defined as AXI4-full.
I write three 32-bit numbers (mem[j] = j). The two writes go fine but the third one gets a BRESP as DECERR.
Waveform shows OVERFLOW (outstanding transaction limit per ID reached).
Is this a MIG issue or an AXI issue? Where does the limit 2 come from? Is the solution to lower the outstanding writes on HLS through a pragma directive?
05-30-2018 07:51 PM
Hi! I also have this problem when I write data to DDR using xdma axi4 interface, the write response is no error. so what's that overflow meaning and when it will happen?
06-07-2018 04:25 AM
This seems to be caused by an ILA parameter which is not automatically propagated from the AXI bus.