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raymond715
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Registered: ‎10-12-2019

[ZCU102 + HLS] Loss data when custom IP write to PL DDR4 by MIG

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Hi, I'm beginner to fpga. I try to write data to PL DDR4 by MIG. In my block design, I add PS, my custom IP, MIG (DDR4) and other IP which is automatically generate by vivado. Details shown below. 

design_block.png

In my test, PS send 512 unsigned int to custom IP (float data, 0 ~ 512, transfer as unsigned int, so for the correct data transfer, first data should be 0x0000_0000 and second should be 0x3f80_0000 however the first data I get in SDK is 0x4180_0000 which is 16 in float form). Custom IP write data to DDR4 by a m_axi port, and then read data from DDR4 by the same port (test if I have set MIG correctly). Then custom IP transfer data to PS. 

The problem is I loss first 16 unsigned int when I read data by MIG (DDR4) and I cannot find reason. I am not sure if I have write first 16 unsigned int to DDR4 successfully. I mapped m_axi port to 0x8000_0000 and in my HLS src, array index start at 16, because I guess that maybe DDR4 cannot use first 512 bits correctly (obviously it is not the reason or I won't post problem here T_T). HLS src shown below.

hls_src.png

I have tried to use ILA and waveform I get shown below. It is weird that it seems that first 16 data have been written to DDR4 as interconnect_write.wcfg shown and address is correct which is 0x8000_0040, but when custom IP (TestTransfer) try to read from DDR4, what it get from address 0x8000_0040 is 0x4180_0000, as testtransfer_read.wcfg shown. It is also weird that as testtransfer_write.wcfg shown, custom IP (TestTransfer) write first data to address 0x8000_0080. I don't know why it write to 0x8000_0080 first. 

wf_axi_interconnect_read.pngwf_axi_interconnect_write.pngwf_testtransfer_read.pngwf_testtransfer_write.png

Any suggestions? I am not good at English and I hope I have stated my problem clearly. Thanks for your time! 

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raymond715
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Registered: ‎10-12-2019

Well, I think I solved the problem of data loss. It seems that I didn't add TLAST signal in input_stream port in custom IP. I can get all data now, but I am facing a new weird problem. I will open a new branch for this T_T.

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raymond715
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Registered: ‎10-12-2019

Well, I found that if I add TLAST port in my custom IP, I won't loss first 16 data. But, now, I will get one wrong data after I get three correct data. Still don't know why...

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raymond715
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Registered: ‎10-12-2019

Data read from DDR4 is wrong. Still don't know why

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raymond715
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409 Views
Registered: ‎10-12-2019

Well, I think I solved the problem of data loss. It seems that I didn't add TLAST signal in input_stream port in custom IP. I can get all data now, but I am facing a new weird problem. I will open a new branch for this T_T.

View solution in original post

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