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Observer
Observer
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Registered: ‎09-20-2018

ZYNQ Ultrascale+ MPSOC with 16-bit width DDR4 problem

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Hi,

    From vivado 2019.1, zynq mpsoc PS support 16-bit width DDR4 memory interface, we verified this configuration in ZCU102 and ZCU104, they work well. So we design our board use mpsoc with one x16 DDR4 component, but it work abnormal, ps boot failed. After a hard time of hardware debugging, we didn't find anything wrong in our desige.

    Then I make 2 new projects to compare the DDR4 configurations: The 1st project choose ZCU104 board, the 2nd project choose xczu2 component, both projects have same DDR4 16-bit width configuration that I can see in the vivado block design, which is below:image.pngimage.png

And there are difference in hdf file between 2 projects:

In psu_init.c, psu_init_gpl.c:

PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x01010101U);  //ZU component project
PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U);  //ZCU EVM project


PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x0F0F0101U);
PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x0F0F0000U);


PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00001F00U);
PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00001F06U);

In psu_init.tcl:

mask_write 0XFD070208 0x0F0F0F0F 0x01010101  //ZU component project
mask_write 0XFD070208 0x0F0F0F0F 0x00000000  //ZCU EVM project


mask_write 0XFD07020C 0x0F0F0F0F 0x0F0F0101
mask_write 0XFD07020C 0x0F0F0F0F 0x0F0F0000


mask_write 0XFD070220 0x00001F1F 0x00001F00
mask_write 0XFD070220 0x00001F1F 0x00001F06

    The ZU component project's file contents are same with our board project's, so I modified those to be same with  ZCU EVM project's, then our board work well.

    Further more, I save the 2 projects' PS Presets configuration tcl file and compare, the key different is:

CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {1}     //ZU component project

CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0}     //ZCU EVM project

    Modified those content and regenerate hdf file, psu_init.c, psu_init_gpl.c, psu_init.tcl are all correct. 

    I can't find any where in vivado block design to modify PS CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0}. Recentlly I tried those in vivado 2019.2, problem is the same.

    Is there anything wrong with my operation? Or is this a vivado bug?

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Moderator
Moderator
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Registered: ‎01-09-2019

Re: ZYNQ Ultrascale+ MPSOC with 16-bit width DDR4 problem

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@xiehuabiao 

Hello,

That parameter should be accessible via the TCL command to adjust any of the configuration parameters for the Zynq, or you can change that in the properties tab of the Block Properties.  Otherwise the manual hack of the psu_init files will work to change that setting as well.

TCL command:

set_property CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING 0 [get_bd_cells zynq_ultra_ps_e_0 ]

I am interested in how you say that you have a failure to boot the PS with this setting turned on.  It normally should only change the order of the Address bits allowing for potentially better performance.

Thanks,
Caleb
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Moderator
Moderator
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Registered: ‎01-09-2019

Re: ZYNQ Ultrascale+ MPSOC with 16-bit width DDR4 problem

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@xiehuabiao 

Hello,

That parameter should be accessible via the TCL command to adjust any of the configuration parameters for the Zynq, or you can change that in the properties tab of the Block Properties.  Otherwise the manual hack of the psu_init files will work to change that setting as well.

TCL command:

set_property CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING 0 [get_bd_cells zynq_ultra_ps_e_0 ]

I am interested in how you say that you have a failure to boot the PS with this setting turned on.  It normally should only change the order of the Address bits allowing for potentially better performance.

Thanks,
Caleb
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