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Visitor m_mansoori
Visitor
181 Views
Registered: ‎11-02-2018

ZedBoard DDR timing issue

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Hi everyone,

I have designed an IP by Vivado HLS and evaluated it in ZedBoard. The design is as follows:

First, the PL reads some data from the DDR3 memory, and after processing the data, it writes them back to DDR3. I used 2 AXI master ports for the inputs of the HLS block, which are connected to 2 HP ports in the PS. The first port reads from the address 0x00000000 and the second port reads from 0x10000000. the output (an array of 32 bits float) is another AXI master port which is connected to the first HP port (with address 0x00000000) by using an AXI smartconnect (details in the figure).Problem.PNG

In the SDK, I write some data in the DDR (in the corresponding addresses), and then activate the HLS block, then I wait until the PL writes the results in the memory. Finally, I read the final results from DDR.

The problem is when the PL finishes writing the output (IsDone), I have to wait for some time before reading from memory (by using an empty for loop), otherwise the results are not correct.

Here is the SDK code:

long long int a1[N],a2[N];
float *ptr=0;
float b[Data_ROWS][Data_COLS];

int addr;
int Offset1=0;
int Offset2=0x10000000;

  addr=Offset1;
    for(int i=0;i<N;i++){
    	Xil_Out64(addr,a1[i]);
    	addr+=8;
            }

    addr=Offset2;
    for(int i=0;i<N;i++){
    	Xil_Out64(addr,a2[i]);
    	addr+=8;
            }

    Xil_DCacheFlush();
    XExample_Initialize(&hls_block,XPAR_EXAMPLE_0_DEVICE_ID);
    while(!XExample_IsReady(&hls_block));
    XExample_Start(&hls_block);
    while(XExample_IsDone(&hls_block));

////    wait_clk(M);

    for(int i=0;i<Data_ROWS;i++){
    	for(int j=0;j<Data_COLS;j++){
    		b[i][j]=*ptr++;
    	}

	}

    for(int i=0;i<Data_ROWS;i++){
    	for(int j=0;j<Data_COLS;j++){
       		printf("Out[%d][%d] = %f\n",i,j,b[i][j]);
       }

Without the "wait_clk(M)" function (which is only an empty "for loop" with M iteration, M= about 54000), I don't get the correct results.

I would really appreciate if anybody can help.

 

Thanks in advance!

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1 Solution

Accepted Solutions
Visitor m_mansoori
Visitor
84 Views
Registered: ‎11-02-2018

Re: ZedBoard DDR timing issue

Jump to solution

I solved the problem.

The reason for the delay was ap_done signal. My HLS code contains two subfunctions and one of them writes the final results to DDR memory. When I used this line in SDK:

while(XExample_IsDone(&hls_block));

It checks the ap_done signal in the top-level function, which is activated right after the configuration of two subfunctions (and before the execution of subfunctions).

So in HLS, I added a 1-bit signal (ap_int<1> done) as the return value of both the subfunction and the top-level function. When the subfunction finishes writing to the memory, it changes the value of done to '1' (done='1'); otherwise done='0'.

The done signal is integrated into the S_AxiLite interface and we have to wait until the received done signal is '1':

while(!XExample_Get_ARG(&hls_block));

These changes fixed the issue and now everything works fine!

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2 Replies
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Scholar drjohnsmith
Scholar
165 Views
Registered: ‎07-09-2009

Re: ZedBoard DDR timing issue ( in the software )

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Just to highlight,

    timming normaly means the XDC file, and meeting the routing requirments,

      this is a software loop problem,  in the software,

I have updated the title on this reply , in hope it stears others with th eright skill set to help you

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Visitor m_mansoori
Visitor
85 Views
Registered: ‎11-02-2018

Re: ZedBoard DDR timing issue

Jump to solution

I solved the problem.

The reason for the delay was ap_done signal. My HLS code contains two subfunctions and one of them writes the final results to DDR memory. When I used this line in SDK:

while(XExample_IsDone(&hls_block));

It checks the ap_done signal in the top-level function, which is activated right after the configuration of two subfunctions (and before the execution of subfunctions).

So in HLS, I added a 1-bit signal (ap_int<1> done) as the return value of both the subfunction and the top-level function. When the subfunction finishes writing to the memory, it changes the value of done to '1' (done='1'); otherwise done='0'.

The done signal is integrated into the S_AxiLite interface and we have to wait until the received done signal is '1':

while(!XExample_Get_ARG(&hls_block));

These changes fixed the issue and now everything works fine!

0 Kudos