Zynq 7000: How to Debug DDR Controller PHY (DDRP) (for a custom Board)

[imbilal_1998]

Hi There!

In a custom made (Based on Zynq 7000 Series) Board, I ran the DDR Training but have no way to confirm that the DDR Training was successful or not. The code is working with OCM but it does not work with DDR (get stucks somewhere) so I know there is an issue with DDR.

Now, I want to debug the issue. I want to know if the DDR Training was successful or not?

So my question is, DDR PHY (DDRP) Controller is responsible for communicating with DRAM, So which register can tell me whether the training was successful or not. Further that, Which other registers can help me in Debugging this issues and How can they help?

By the way I am using DDR3.

Thanks,

Bilal

[rpr]

Hi @imbilal_1998 

Please see the inline comments:

In a custom made (Based on Zynq 7000 Series) Board, I ran the DDR Training but have no way to confirm that the DDR Training was successful or not. The code is working with OCM but it does not work with DDR (get stucks somewhere) so I know there is an issue with DDR.

Now, I want to debug the issue. I want to know if the DDR Training was successful or not?

-> OCM is on chip memory and DDR3 is external memory device, how training happened over OCM? i didnt get you what you are looking for.

So my question is, DDR PHY (DDRP) Controller is responsible for communicating with DRAM, So which register can tell me whether the training was successful or not. Further that, Which other registers can help me in Debugging this issues and How can they help?

By the way I am using DDR3.

-> On your custom board, are you looking for xilinx memory interface generator like "contoller & PHY or PHY only" to interface externla DDR3 memory device ?

Xilinx MIG, information is documented in ug586, link provided below.

https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf

MIG 7 series PHY only, please go through the following links.

https://www.xilinx.com/support/answers/51204.html

https://www.xilinx.com/Attachment/51204/Xilinx_Answer_51204.pdf