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Registered: ‎04-19-2016

Zynq-7000 low power part ECC (72bit) support

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*I selected part XC7Z100-L2FFG900I, and try to configure a MIG ip for a 64-bit DDR3 interface with 8-bit ECC, totaly 72bit. 

*However, received below error, that is selected width cannot be achieved with the selected FPGA device and memory component. Switch to a larger FPGA device. 

* So this FPGA is the largest one of the Zynq-7000 series. This part is really not support the ECC options?  This part is a low power one. 

*I read Zynq datasheet, mig datasheet and there is not written anything about the low power parts does not support the ECC options in MIG IP.


Best Regards,

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Registered: ‎02-24-2014

You need to switch to the 1156 pin package for a DDR3 memory that big.   72 bits needs 3 full adjacent IO banks, and the 900 pin package doesn't quite have enough.  If you look at the 900 pin package pinout,  a whole lot of IO is eaten by the GTX serdes and the PS fixed pins.


Edit:  My mistake.   It does support it, albeit at a lower clock speed.   you've found one of the many cases where the documentation doesn't match the software.

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Registered: ‎04-19-2016



*For XC7Z100-L2FFG900I --> The Error is disappeared, after I decreased the DDR3 clock frequency to 533MHz with ECC enable, as seen below. However -2LI speed grade low power part support 1600 Mb/s via HP port that is written in the DS191, Table 53. Ok, then maybe this data rate could be without ECC option. But this case is not specified anywhere in both Zynq and MIG docs. 


*For XC7Z045-2FFG900I --> In this part, MIG accepts the 800MHz DDR3 clock frequency with ECC options enabled ( 72bit). So, it is not related to package pin number as you said.


*So, It is seen that Low power parts support ECC options enabled (72bit) DDR3 interface up to 533MHz. And this case is not written anywhere until we realized. 


*Below highlighted DS191 sentence is not correct for ECC enabled DDR3 interface case (72bit) in the -2LI speed grade devices?

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Registered: ‎07-23-2015

@doner_t We are looking into this and will update you soon. 

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Registered: ‎11-28-2016

Hello @doner_t,


Sorry for the delay but it took some time for me to narrow down the behaviors we're seeing with the MIG GUI.


When you select the FFG900 -2L part the tools decide that there's no way to fit that interface in to the High Performance banks and places it in the High Range banks. This seems to be a false assumption done by the tools.  If you select a normal speed grade device it will automatically place a full speed DDR3 x72 interface in the High Performance banks.  For the Low Power devices the tools consider the limitations of AR#50739 to mean that this type of interface can't fit in the HP banks.  However when you select a normal speed grade device it places the interface in the HP banks because it uses a bit more intelligence.  Unfortunately the MIG GUI won't let you advance to do a Fixed Pinout configuration for a high speed x72 interface because it's already under the assumption that it won't fit in the HP banks regardless of the intelligence used while making the pinout.

When you select a low power FFx/RFx 676 package it doesn't allow you to configure any x72 interface because these packages don't have the same amount of HR banks like the FFx/RFx 900 packages, and because of the earlier behavior of AR#50739 the tools didn't have the intelligence to know that this type of interface should fit in the HP banks if you do it correctly.


I created a CR to address this behavior.  Hopefully it's simply making sure that the Low Power devices use the intelligence to auto place these large interfaces in the High Performance banks.


In the meantime if you want to do pin planning and stuff like that you can select the equivalent normal speed grade part.