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bogdan.deac
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Registered: ‎04-19-2017

Zynq DDR compatibility issues

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Hello,

We have two custom Zynq-based boards. The only difference between the two is the DDR memory. One board has 512MB MT41K128M16JT-125 memory and the other one has 1024MB MT41K256M16TW-107 memory. The same PCB was used for the both boards.The boards have component-based DDR interface.

We performed the following tests:

  1. We configured Zynq with parameters for 512MB memory. This memory has 14 Row Address Count (Bits). If we run Zynq DRAM tests from SDK on 512MB memory board, '5' - Test 511MB length from address 0x100000 terminates with no errors.
  2. If we use the same configuration on the 1024MB memroy board, the same test generates the following output:

 

Starting Memory Test '5' - Testing 511MB length from address 0x100000...
------------------------------------------------------------------------------------------
    TEST           WORD ERROR             PER-BYTE-LANE ERROR COUNT              TIME
                     COUNT        [ LANE-0 ] [ LANE-1 ] [ LANE-2 ] [ LANE-3 ]    (sec)
------------------------------------------------------------------------------------------
Memtest_0 (  0: 0)      5750         [    4232] [    4231] [    2784] [    1001]    7.94316
Memtest_s (  0: 1)      4163         [    3072] [    3072] [    2691] [    1004]    3.19095
Memtest_s (  0: 2)      15257865         [   81473] [       6] [13697564] [12016842]    13.0929
Memtest_s (  0: 3)      2578         [    2048] [    2048] [    1201] [    1002]    3.20156
Memtest_s (  0: 4)      7132         [    6144] [    6144] [    1004] [    1004]    3.19862
Memtest_s (  0: 5)      5542         [    4497] [    4460] [    1016] [    1001]    3.20039
Memtest_s (  0: 6)      2118         [    1268] [    1266] [    1004] [    1004]    3.19685
Memtest_s (  0: 7)      9904         [    9216] [    9216] [    1032] [    1001]    3.20097
Memtest_s (  0: 8)      2028         [    1024] [    1024] [    1004] [    1004]    3.19567
Memtest_p (  0: 9)      2480         [    1010] [    1001] [    1819] [    1676]    7.44594
Memtest_p (  0:10)      1560         [    1024] [    1024] [    1001] [    1001]    7.44535
Memtest_l (  0:11)      1868         [    1020] [    1020] [    1001] [    1001]    8.14134
Memtest_l (  0:12)      1982         [    1022] [    1022] [    1001] [    1002]    8.14134
Memtest_l (  0:13)      2026         [    1021] [    1021] [    1001] [    1002]    8.14134
Memtest_l (  0:14)      1960         [    1021] [    1021] [    1004] [    1001]    8.14134

The 1024MB memory has 15 Row Address Count (Bits). The most significant bit (bit 14) is driven low when the 1024MB memory board is loaded with the 512MB memory configuration.

We have consulted Xilinx's solution regarding this issue. It is not valid in our case because we don't use DIMMs and, despite the MIG, the Zynq DDR controller drives low the unused address signals.

 

Is it possible to run a project configured to use 512MB memory on a platform that has 1024MB memory? Did we configure something wrong?

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ryana
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Registered: ‎11-28-2016

Hello @bogdan.deac ,

I think I've already answered this question somewhere else but the issue is with using the timing parameters for the smaller device while talking to the larger device.  Everything has an equivalent operating point so most of your settings are good but the problem here is with tRFC.  The smaller device has a smaller tRFC while the larger device requires a larger tRFC.  When you use the settings from the smaller device on the larger device you violate tRFC which will cause errors.  To work around this I would either use the settings for the larger memory device in both a applications or manually modify the tRFC value in the output products of the smaller device application build and use it in both designs.

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kren
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Registered: ‎08-21-2007

You should created two projects/controllers seperatedly for the two memory parts, as the address width is different.

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bogdan.deac
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Registered: ‎04-19-2017

Thanks for reply. Could you provide more details? I do not understand why it is not possible to use only 512MB out of 1024MB memory if the DDR controller is configured with 512MB parametrs. The 15th bit from the address bus is driven low by the memory controller. We have many binary projects released for 512MB memory-based board. Now we would like to upgrade the memory to 1024MB but we are stucked because the projects do not work on the upgraded version. Do we need to regenerate the projects with a new DDR controller configuration?

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kren
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Registered: ‎08-21-2007

Sorry, I misunderstood. You can use only 512MB out of 1024MB memory if the DDR controller is configured with 512MB parametrs.

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bogdan.deac
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Registered: ‎04-19-2017

That's what we are trying to do. But if we configure the Zynq DDR controller with 512MB memory parameters we get the above mentioned errors when we run the DDR check test project.

Belowis the the DDR configuration that we applied to a dev. board that has 1024MB DDR memory. The configuration should set Zynq to use only 512MB out of 1024MB but the DDR check test fails as I mentioned above.

 

 

DDR_512MB_Config.PNG

Did we missed something? Why does the projects configured for 512MB DDR memory fail when they run on 1024MB DDR memory?

 

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ryana
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Registered: ‎11-28-2016

Hello @bogdan.deac ,

I think I've already answered this question somewhere else but the issue is with using the timing parameters for the smaller device while talking to the larger device.  Everything has an equivalent operating point so most of your settings are good but the problem here is with tRFC.  The smaller device has a smaller tRFC while the larger device requires a larger tRFC.  When you use the settings from the smaller device on the larger device you violate tRFC which will cause errors.  To work around this I would either use the settings for the larger memory device in both a applications or manually modify the tRFC value in the output products of the smaller device application build and use it in both designs.

View solution in original post

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