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Registered: ‎05-06-2018

Zynq MIG DDR3 pin allocation problem.

Hi All

I am working on XC7X020-2CLG484I, and i am going to need 2 unit of MT41J256M16HA-125 DDR3.  I have included the MIG for these DDR3 configuration, but cant seem able to allocate the address to the correct bytegroup(Tn). Under the MIG Bank Selection, I am going to use BANK 13 for RAM_0 and BANK 33 for RAM_1.

Under the dropdown signal set, I got Address/Ctrl-0, Address/Ctrl-1, Address/Ctrl-2, DQ[0-7].

Look at the datasheet, I should need to have DQ[0-7] and DQ[8-15], so I have increase the datawidth to [16]. But now I am having 5 choices under the signal set dropdown menu, Address/Ctrl-0, Address/Ctrl-1, Address/Ctrl-2, DQ[0-7], DQ[8-15]. But I only have 4 byte groups to assign for. The MT41J256M16HA-125 has A0-A15, so assume that I should be having 2 set of Address/Ctrl only, how can I reduce it to 2 for [A0~A15].

*Error:  Memory Signals must be allocated within 3 vertical banks of the same column. 

Can someone please guide me on connecting the 2xMT41J256M16HA-125 using the MIG?  One on bank 13 and bank 33? 


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Xilinx Employee
Xilinx Employee
Registered: ‎02-21-2019

Hello @ chchyong89 

The reason you are seeing that error is because Bank 13 and 33 are in different FPGA I/O column. Here is a screenshot referencing this for XC7Z020CLG484 from Zynq 7000 Package and Planning Pinout in UG865:  


Now, you can use a single x32 bit DDR3 interface as shown below:  


All the address, control and data pins are allocated in Bank 34 and Bank 35 that are in a single FPGA I/O column and comply as also noted from UG865.  


If you are trying to use 2 separate x16 DDR3 interfaces, as you can see above, this package does not have enough pins to support the configuration. 

Note: A single instance of MIG IP can generate a memory interface width up to 72 bits. Based on the description of your memory topology it makes the most sense to generate a single IP core with a x32 data width.   

Here is a link to Zynq 7000 Pkg Pinout for your reference.  

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