Zynq MPSoC Ultrascale+ PS using SRAM for heap, stack, data and code sections
We are having trouble finding a way to connect SRAM to the PS. Let me explain it a bit:
In our team, we are designing a custom board, and one of the requisites is to use SRAM memory for the processor (not DRAM or SDRAM). So, in IP Integrator we instantiate an External Memory Controller core to handle an external SRAM. We have to use a Synchronous SRAM, and the EMC generates the interface for a Standard Synchronous SRAM. But, taking a look at the market, Synchronous SRAMs working at 1,8V are mostly QDRII+, QDRIV or DDR-II, not Standard. And the EMC doesn´t seem to have the possibility to select QDR or DDR Sync SRAM, and choosing Sync SRAM does not generate the adequate ports for a QDR/DDR SRAM.
On the other hand, outside the IPI, there are cores based on MIG to handle QDRIV/QDRII+ SRAM memories, but they don´t seem to be able to connect to the PS and the AXI.
So, my question is:
Is there a way to use an external Synchronous SRAM (not Standard) for placing heap, stack, data and code sections, that is, so the PS interacts with it? A way to connect the SRAM to the AXI so the linker script can be generated taking into account this memory? Or, at least, is there any kind of Standard Synchronous SRAM in the market available, working at 1,8V?