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Visitor
Visitor
1,005 Views
Registered: ‎04-09-2010

Zynq PS DDR in clamshel

Hello,

We are developing a board with a Zynq UltraScale+ MPSoC and we want to use DDR4 chips with the PL and PS, both in a clamshell topology. We know that the PS DDR interface doesn't have this as a configuration option, but the UG583 (v1.17) say that it is possible to use this topology with the PS if we set up the PS DDR as dual-rank and mirror the second rank on the bottom layer of the PCB.

We have made some assumptions about this subject but we are not sure if they are right. Can you please confirm that the following assumptions that we made are right?

 

1º In the PS DDR configuration we need to select the “Dual-Rank” and “Address Mirroring” option.

2º The memory chips at the top layer (first rank) of the PCB must connect to the FPGA normally.

3º The memory chips at the bottom layer (second rank) of the PCB must have some address pins mirrored as stated in the table 2-10 of the UG583.

4º Because with the PS we treat the memories as dual-rank, the CKE and ODT appears doubled. In this case CKE[0] and ODT[0] must connect to first rank (top layer of PCB) of memories and CKE[1] and ODT[1] must connect to second rank (bottom layer of PCB) of memories.

5º CS[0] and CS[1] signals must connect to first rank and second rank, respectively.

 

Are these assumptions right? Are we forgetting something?

 

Thanks in advanced,

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6 Replies
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Xilinx Employee
Xilinx Employee
929 Views
Registered: ‎03-14-2016

Hello,

Your assumptions are correct.

1. Make sure you have selected "Dual Rank" and "Address Mirroring".  The "Address Mirroring" check box should automacally be checked when you first select "Dual Rank".

2. Connect the top layer as the first rank (Rank 0), connect all signals to FPGA as indicated in UG1075, v1.8, Table 2-2 for 2 Rank.  Use CK_t/c[0], CS_n[0] and CKE[0].  Address pins connected normally (UG583, v1.17, Table 2-10, non-mirrored). 

3. The chips on the bottom layer are your second rank (Rank 1).  Connect signals accorting to UG1075, Table 2-2 for 2 Rank.  Use CK_t/c[1], CS_n[1] and CKE[1] Address pins connected mirrored (UG583, Table 2-10, mirrored).

Items 4 and 5 are correct.

Thank you,
Sam

 

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Xilinx Employee
Xilinx Employee
918 Views
Registered: ‎03-14-2016

Please note that there are two ODT signals, connect ODT in the same manner.

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Visitor
Visitor
884 Views
Registered: ‎04-09-2010

Hi samhendr,

Thank you for your reply. It´s was very useful and reassure for us.
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Observer
Observer
382 Views
Registered: ‎12-04-2018

@samhendr @pedro.neves 

Sir, We have one of the boards, where DDR4 (4Gb) chip with PS controller has been used.

The design is clamshell but we do not have Rank concept, we use single CS0 for all 4 chips [Top and Bottom] and also single ODT0.

We have tried x64 Configuration, but we are stuck at psu_init, write leveling error.

Please help us with your feedback, we are in a difficult scenario. 

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Xilinx Employee
Xilinx Employee
377 Views
Registered: ‎03-14-2016

Hello,

Can you please tell me more about your setup

I'm looking for your settings in the processor configuration wizard (PCW).  Do you have Dual Rank selected?

On your schematic are you performing address mirroring?

Thank you,

Sam

 

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Observer
Observer
369 Views
Registered: ‎12-04-2018

@samhendr 

We have not selected Dual Rank, as we have single chip select for all 4 DDR chips, and we do not have any Address Mirroring.

Please find the PCW for both 1600 and 2400 MHz

 

DDR4_x16_1600L.jpg
DDR4_x64_2400U.jpg
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