10-01-2019 07:47 AM
We are developing a board with a Zynq UltraScale+ MPSoC and we want to use DDR4 chips with the PL and PS, both in a clamshell topology. We know that the PS DDR interface doesn't have this as a configuration option, but the UG583 (v1.17) say that it is possible to use this topology with the PS if we set up the PS DDR as dual-rank and mirror the second rank on the bottom layer of the PCB.
We have made some assumptions about this subject but we are not sure if they are right. Can you please confirm that the following assumptions that we made are right?
1º In the PS DDR configuration we need to select the “Dual-Rank” and “Address Mirroring” option.
2º The memory chips at the top layer (first rank) of the PCB must connect to the FPGA normally.
3º The memory chips at the bottom layer (second rank) of the PCB must have some address pins mirrored as stated in the table 2-10 of the UG583.
4º Because with the PS we treat the memories as dual-rank, the CKE and ODT appears doubled. In this case CKE and ODT must connect to first rank (top layer of PCB) of memories and CKE and ODT must connect to second rank (bottom layer of PCB) of memories.
5º CS and CS signals must connect to first rank and second rank, respectively.
Are these assumptions right? Are we forgetting something?
Thanks in advanced,
10-07-2019 11:38 AM
Your assumptions are correct.
1. Make sure you have selected "Dual Rank" and "Address Mirroring". The "Address Mirroring" check box should automacally be checked when you first select "Dual Rank".
2. Connect the top layer as the first rank (Rank 0), connect all signals to FPGA as indicated in UG1075, v1.8, Table 2-2 for 2 Rank. Use CK_t/c, CS_n and CKE. Address pins connected normally (UG583, v1.17, Table 2-10, non-mirrored).
3. The chips on the bottom layer are your second rank (Rank 1). Connect signals accorting to UG1075, Table 2-2 for 2 Rank. Use CK_t/c, CS_n and CKE Address pins connected mirrored (UG583, Table 2-10, mirrored).
Items 4 and 5 are correct.
07-29-2020 01:54 PM
Sir, We have one of the boards, where DDR4 (4Gb) chip with PS controller has been used.
The design is clamshell but we do not have Rank concept, we use single CS0 for all 4 chips [Top and Bottom] and also single ODT0.
We have tried x64 Configuration, but we are stuck at psu_init, write leveling error.
Please help us with your feedback, we are in a difficult scenario.
07-29-2020 02:07 PM
Can you please tell me more about your setup
I'm looking for your settings in the processor configuration wizard (PCW). Do you have Dual Rank selected?
On your schematic are you performing address mirroring?
07-29-2020 02:12 PM