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Registered: ‎10-18-2019

Zynq UltraScale+: DDR calibration issue


I am working on custom boards implementing Zynq Ultrascale+ MPSoC. On most of these boards, I have no problem running our application but on a very few, the following issue appear when trying to flash via QSPI on the SDK.

Capture du 2019-12-03 16-04-54.png

When I launch the debug, I see that the FSBL initialization process is stuck in a PUB_PGSR0 register related loop. Then the issue seems to be coming from DDR calibration.
We use 5 DDR chips from Micron including one for ECC, reference MT40A512M16JY-083 IT:B. The DDR configuration on Vivado is as follows.


(The ECC is actually enabled here, the default ECC field value I used for DDR configuration is not disabled)


When I change the DRAM Bus width from 64 to 32 bits and disable the ECC, it works fine on a defective board. However, when I keep a 32 bits DRAM bus width and enable the ECC, the initialization issue appears again.

Plus, when I try different DDR configurations (changing DRAM bus width, enabling DBI..) all work on the functional board except when I set the DRAM Bus width to 64 bits and disable ECC. This last configuration generates the same DDR calibration error on "functional" and "defective" boards.

Does anyone have some idea on what might be to root of the issue here, and how to correct it ?



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Registered: ‎01-09-2019

Hello @kmoukoko 

The first thing I noticed about your configuration is that it is setup for a 2400P part, but the device you have defined is a 2400T part (the -083 speed) which means you should have a CAS Latency of 17 not 16.  It looks like you configured the design for a -083E speed grade which the part you mentioned is a -083 speed grade.  This means that the tRP/tRCD/tRC are incorrect for the part you are using and should be adjusted (tRC should be 45.16, tRP=tRCD=17).

When you say that running a 32 bit interface makes the interface run, but running with the full 64 bit or 64+ECC does not, that indicates to me that something might not be correct in your routing for the upper bytes.  Getting register dumps from the PS DDR registers would be helpful if the above changes in configuration does not fix your issues.

We have guidelines for a working memory interface routing.  Have you gone through all the guidelines in UG583 for Memory Interfaces (chapter 2: )?  I would double check through the general guidelines starting on page 49.  One common mistake is to not have enough ground stitching which can have significant impact on signal performance (see pages 57-58 for more detail).

Don’t forget to reply, kudo, and accept as solution.