10-11-2019 03:35 AM
In UG583 (v1.17), table 2-45, the CK to DQS skew-constraint is given as a single value: 500ps. For other types of DDR, this skew constraint is given as a range of acceptable values.
Could you explain please - is this a mistake? It seems wrong to tune our trace-delays to hit one specific large delay such as this.
The PS LPDDR4 PHY can run a up to 2400Mbs, at which frequency a skew of 500ps is greater than a bit-cell in duration. This is confusing, and so I need some clarification.
What CK to DQS skew is needed for PS LPDDR4?
10-17-2019 03:10 AM
10-28-2019 08:29 AM
Any help at all from Xilinx on this would be appreciated.
If you don't know, please say so, so I can move on.